ADSP-21486KSWZ-2AB datasheet(30/68 Pages) AD

30 / 68 page

Rev. B

Page 30 of 68

March 2013

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers), there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 29. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

tPCGIW

Input Clock Period

tPCLK × 4

tSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input

Clock

4.5

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3ns

Switching Characteristics

tDPCGIO

PCG Output Clock and Frame Sync Active Edge

Delay After PCG Input Clock

2.5

tDTRIGCLK

PCG Output Clock Delay After PCG Trigger

2.5 + (2.5 × tPCGIP)

10 + (2.5 × tPCGIP)ns

tDTRIGFS

PCG Frame Sync Delay After PCG Trigger

2.5 + ((2.5 + D – PH) × tPCGIP)

10 + ((2.5 + D – PH) × tPCGIP)ns

tPCGOW

Output Clock Period

2 × tPCGIP – 1

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

1 Normal mode of operation.

Figure 16. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCG_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG

tHTRIG

tPCGOW

tDPCGIO

tPCGIP

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