Rev. B

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Page 32 of 68

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March 2013

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SDRAM Interface Timing (166 MHz SDCLK)

The maximum frequency for SDRAM is 166 MHz. For informa-

tion on SDRAM frequency and programming, see the

ADSP-214xx SHARC Processor Hardware Reference, Engineer-

to-Engineer Note “Interfacing SDRAM Memories to SHARC

Processors” (EE-286), and the SDRAM vendor data sheet.

Table 31. SDRAM Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

DATA Setup Before SDCLK

0.7

ns

DATA Hold After SDCLK

1.23

ns

Switching Characteristics

1

SDCLK Period

6

ns

SDCLK Width High

2.2

ns

SDCLK Width Low

2.2

ns

2

Command, ADDR, Data Delay After SDCLK

4

ns

2

Command, ADDR, Data Hold After SDCLK

1

ns

Data Disable After SDCLK

5.3

ns

Data Enable After SDCLK

0.3

ns

SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM Memories to SHARC Processors” (EE-286) for

more information on hardware design guidelines for the SDRAM interface.

Figure 18. SDRAM Interface Timing

SDCLK

DATA (IN)

DATA (OUT)

COMMAND/ADDR

(OUT)