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ADSP-21486KSWZ-2AB 数据表(PDF) 51 Page - Analog Devices

部件名 ADSP-21486KSWZ-2AB
功能描述  SHARC Processor
PDF  68 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-21486KSWZ-2AB 数据表(HTML) 51 Page - Analog Devices

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B
|
Page 51 of 68
|
March 2013
Media Local Bus
All the numbers given are applicable for all speed modes
(1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for
5-pin), unless otherwise specified. Please refer to the MediaLB
specification document revision 3.0 for more details.
Table 52. MLB Interface, 3-Pin Specifications
Parameter
Min
Typ
Max
Unit
3-Pin Characteristics
tMLBCLK
MLB Clock Period
1024 FS
512 FS
256 FS
20.3
40
81
ns
ns
ns
tMCKL
MLBCLK Low Time
1024 FS
512 FS
256 FS
6.1
14
30
ns
ns
ns
tMCKH
MLBCLK High Time
1024 FS
512 FS
256 FS
9.3
14
30
ns
ns
ns
tMCKR
MLBCLK Rise Time (VIL to VIH)
1024 FS
512 FS/256 FS
1
3
ns
ns
tMCKF
MLBCLK Fall Time (VIH to VIL)
1024 FS
512 FS/256 FS
1
3
ns
ns
tMPWV
1
MLBCLK Pulse Width Variation
1024 FS
512 FS/256
0.7
2.0
nspp
nspp
tDSMCF
DAT/SIG Input Setup Time
1
ns
tDHMCF
DAT/SIG Input Hold Time
2
ns
tMCFDZ
DAT/SIG Output Time to Three-state
0
15
ns
tMCDRV
DAT/SIG Output Data Delay From MLBCLK Rising Edge
8
ns
tMDZH
2
Bus Hold Time
1024 FS
512 FS/256
2
4
ns
ns
CMLB
DAT/SIG Pin Load
1024 FS
512 FS/256
40
60
pf
pf
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2 The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
minimized while meeting the maximum capacitive load listed.



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