1–16

Chapter 1: Cyclone III Device Datasheet

Switching Characteristics

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 2

Embedded Multiplier Specifications

Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.

Memory Block Specifications

Table 1–22 describes the M9K memory block specifications for Cyclone III devices.

Configuration and JTAG Specifications

Table 1–23 lists the configuration mode specifications for Cyclone III devices.

scanclk

frequency

—

—

100

MHz

Notes to Table 1–20:

(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.

jitter of the PLL, when an input jitter of 30 ps is applied.

(6) With 100 MHz scanclk frequency.

(Part 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Table 1–21. Cyclone III Devices Embedded Multiplier Specifications

Mode

Resources Used

Performance

Unit

Number of Multipliers

C6

C7, I7, A7

C8

9 × 9-bit

multiplier

1

340

300

260

MHz

18 × 18-bit

multiplier

1

287

250

200

MHz

Table 1–22. Cyclone III Devices Memory Block Performance Specifications

Memory

Mode

Resources Used

Performance

LEs

M9K

Memory

C6

C7, I7, A7

C8

Unit

M9K Block

FIFO 256 × 36

47

1

315

274

238

MHz

Single-port 256 × 36

0

1

315

274

238

MHz

Simple dual-port 256 × 36 CLK

0

1

315

274

238

MHz

True dual port 512 × 18 single CLK

0

1

315

274

238

MHz

Table 1–23. Cyclone III Devices Configuration Mode Specifications

Programming Mode

Unit

Passive Serial (PS)

133

MHz

Fast Passive Parallel (FPP) (1)

100

MHz

Note to Table 1–23:

(1) EP3C40 and smaller density members support 133 MHz.