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3.3-VLVCMOS 数据表(PDF) 28 Page - Altera Corporation

部件名 3.3-VLVCMOS
功能描述  This chapterdescribes the electric characteristics, switching characteristics,and I/O timing for Cyclone III devices. A glossary is also included for your reference
PDF  34 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

3.3-VLVCMOS 数据表(HTML) 28 Page - Altera Corporation

Back Button 3.3-VLVCMOS Datasheet HTML 24Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 25Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 26Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 27Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 28Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 29Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 30Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 31Page - Altera Corporation 3.3-VLVCMOS Datasheet HTML 32Page - Altera Corporation Next Button
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Chapter 1: Cyclone III Device Datasheet
Glossary
Cyclone III Device Handbook
July 2012
Altera Corporation
Volume 2
N
——
O
——
P
PLL Block
The following block diagram highlights the PLL Specification parameters.
Q
——
R
RL
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input
Waveform
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
RSKM (Receiver
input skew
margin)
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
Table 1–39. Glossary (Part 2 of 5)
Letter
Term
Definitions
Core Clock
Phase tap
Reconfigurable in User Mode
Key
CLK
N
M
PFD
VCO
CP
LF
CLKOUT Pins
GCLK
fINPFD
fIN
fVCO
fOUT
fOUT _EXT
Switchover
Counters
C0..C4
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID



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