AD7453BRT-R2 datasheet(4/20 Pages) AD

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AD7453

Rev. B | Page 4 of 20

Parameter

Test Conditions/Comments

A Version1

B Version1

Unit

CONVERSION RATE

Conversion Time

1.6 µs with a 10 MHz SCLK

SCLK cycles

Track-and-Hold Acquisition Time2

Sine wave input

250

ns max

Full-scale step input

290

ns max

Throughput Rate

555

kSPS max

POWER REQUIREMENTS

VDD

2.7/5.25

V min/max

IDD7, 8

Normal Mode (Static)

SCLK on or off

0.5

mA typ

Normal Mode (Operational)

VDD = 4.75 V to 5.25 V

1.5

mA max

VDD= 2.7 V to 3.6 V

1.2

mA max

Full Power-Down Mode

SCLK on or off

µA max

Power Dissipation

Normal Mode (Operational)

VDD = 5 V; 1.55 mW typ for 100 kSPS7

7.25

mW max

VDD = 3 V; 0.64 mW typ for 100 kSPS7

3.3

mW max

Full Power-Down Mode

VDD = 5 V; SCLK on or off

µW max

VDD = 3 V; SCLK on or off

µW max

1 Temperature ranges as follows: A, B versions: –40°C to +85°C.

2 See

section.

Terminology

3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

4 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.

5 The AD7453 is functional with a reference input in the range 100 mV to VDD.

6 Guaranteed by characterization.

7 See

section.

Power vs. Throughput Rate

8 Measured with a full-scale dc input.

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