AD7453

Rev. B | Page 13 of 20

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and performance degrades.

Figure 20 shows a graph of the THD versus analog input signal

frequency for different source impedances.

INPUT FREQUENCY (kHz)

–100

10

100

277

–80

–50

–40

0

200

Ω

–10

–20

–30

–60

–70

–90

10

Ω

62

Ω

100

Ω

Figure 20. THD vs. Analog Input Frequency for Various Source Impedances

Figure 21 shows a graph of THD versus analog input frequency

for various supply voltages while sampling at 555 kSPS with an

SCLK of 10 MHz. In this case, the source impedance is 10 Ω.

–90

10

100

277

–85

–80

–75

–70

–65

–60

–55

–50

INPUT FREQUENCY (kHz)

Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages

DIGITAL INPUTS

The digital inputs applied to the AD7453 are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied, i.e., CS and SCLK, can go to 7 V and are

The main advantage of the inputs not being restricted to the

of latch-up as there would be on the analog inputs if a signal

REFERENCE

An external source is required to supply the reference to the

The specified reference is 2.5 V for the 2.7 V to 5.25 V power

supply range. The reference input chosen for an application

should never be greater than the power supply. Errors in the

reference source result in gain errors in the AD7453 transfer

function. A capacitor of at least 0.1 µF should be placed on the

AD780 and the ADR421. Figure 22 shows a typical connection

1

AD780

NC

8

2

NC

7

3

GND

6

4

TEMP

5

OPSEL

TRIM

AD7453*

2.5V

NC

NC

NC = NO CONNECT

10nF

0.1

µF

0.1

µF

0.1

µF

*ADDITIONAL PINS OMITTED FOR CLARITY

SERIAL INTERFACE

Figure 2 shows a detailed timing diagram of the serial interface

of the AD7453. The serial clock provides the conversion clock

and controls the transfer of data from the device during

conversion. CS initiates the conversion process and frames the

data transfer. The falling edge of CS puts the track-and-hold

into hold mode and takes the bus out of three-state. The analog

input is sampled and the conversion is initiated at this point.

The conversion requires 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold

goes back into track mode on the next SCLK rising edge, as

shown at Point B in Figure 2. On the 16th SCLK falling edge, the

SDATA line goes back into three-state.

If the rising edge of CS occurs before 16 SCLKs have elapsed,

the conversion is terminated and the SDATA line goes back into

three-state.

The conversion result from the AD7453 is provided on the

SDATA output as a serial data stream. The bits are clocked out

on the falling edge of the SCLK input. The data stream of the

AD7453 consists of four leading zeros, followed by 12 bits of

conversion data, provided MSB first. The output coding is

straight (natural) binary.