AD9848AKST datasheet(18/32 Pages) AD

18 / 32 page

REV. A

AD9848/AD9849

–18–

Bit

Default

Address

Content

Width

Value

AFE REGISTER BREAKDOWN

Serial Address:

oprmode

[7:0]

8'h0

8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}

[1:0]

2'h0

powerdown[1:0]

Full Power

2'h1

Fast Recovery

2'h2

Reference Standby

2'h3

Total Shutdown

[2]

disblack

Disable Black Loop Clamping (High Active)

[3]

test mode

Test Mode—Should Be Set LOW

[4]

test mode

Test Mode—Should Be Set HIGH

[5]

test mode

Test Mode—Should Be Set LOW

[6]

test mode

Test Mode—Should Be Set LOW

[7]

test mode

Test Mode—Should Be Set LOW

ctlmode

[5:0]

6'h0

Serial Address: 8'h06 {cltmode[5:0]}

[2:0]

3'h0

ctlmode[2:0]

Off

3'h1

Mosaic Separate

3'h2

VD Selected/Mosaic Interlaced

3'h3

Mosaic Repeat

3'h4

Three-Color

3'h5

Three-Color II

3'h6

Four-Color

3'h7

Four-Color II

[3]

enablepxga

Enable PxGA (High Active)

[4]

1'h0

outputlat

Latch Output Data on Selected DOUT Edge

1'h1

Leave Output Latch Transparent

[5]

1'h0

tristateout

ADC Outputs Are Driven

1'h1

ADC Outputs Are Three-Stated

PRECISION TIMING HIGH SPEED TIMING

GENERATION

The AD9848 and AD9849 generate flexible high speed timing

signals using the Precision Timing core. This core is the founda-

tion for generating the timing used for both the CCD and the

AFE; the reset gate RG, horizontal drivers H1–H4, and the

SHP/SHD sample clocks. A unique architecture makes it rou-

tine for the system designer to optimize image quality by

providing precise control over the horizontal CCD readout and

the AFE correlated double sampling.

Timing Resolution

The Precision Timing core uses a 1

master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 4 illustrates how the internal timing

core divides the master clock period into 48 steps or edge posi-

tions. Therefore, the edge resolution of the Precision Timing

core is (tCLI/48). For more information on using the CLI input,

see the Driving the CLI Input section.

High Speed Clock Programmability

Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and

SHD are generated. The RG pulse has programmable rising and

falling edges and may be inverted using the polarity control. The

horizontal clocks H1 and H3 have programmable rising and falling

edges and polarity control. The H2 and H4 clocks are always

inverses of H1 and H3, respectively. Table II summarizes the

high speed timing registers and their parameters.

The edge location registers are six bits wide, but there are only

48 valid edge locations available. Therefore, the register values

are mapped into four quadrants, with each quadrant containing

12 edge locations. Table III shows the correct register values for

the corresponding edge locations. Figure 6 shows the range and

default locations of the high speed clock signals.

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