AD9848AKST datasheet(23/32 Pages) AD

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REV. A

AD9848/AD9849

–23–

Recommended Power-Up Sequence

When the AD9848 and AD9849 are powered up, the following

sequence is recommended (refer to Figure 14 for each step).

1. Turn on power supplies for AD9848/AD9849.

2. Apply the master clock input CLI, VD, and HD.

3. The Precision Timing core must be reset by writing a “0” to the

TGCORE_RSTB Register (Address x026) followed by writing

a “l” to the TGCORE_RSTB Register. This will start the inter-

nal timing core operation. Next, initialize the internal circuitry

by first writing “110101” or “53” decimal to the INITIAL1

mal to the INITIAL2 Register (Address x00F).

4. Write a “1” to the PREVENTUPDATE Register (Address x019).

This will prevent the updating of the serial register data.

5. Write to desired registers to configure high speed timing and

horizontal timing.

6. Write a “1” to the OUT_CONT Register (Address x016). This

will allow the outputs to become active after the next VD/HD

rising edge.

7. Write a “0” to the PREVENTUPDATE Register (Address

x019). This will allow the serial information to be updated

at next VD/HD falling edge.

8. The next VD/HD falling edge allows register updates to occur,

including OUT_CONT, which enables all clock outputs.

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9848/AD9849 signal processing chain is shown in

Figure 15. Each processing step is essential in achieving a high

quality image from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc restore

circuit is used with an external 0.1

µF series coupling capacitor.

This restores the dc level of the CCD signal to approximately 1.5 V

to be compatible with the 3 V analog supply signal of the

AD9848/AD9849.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 6 illustrates how the two internally generated CDS

clocks, SHP and SHD, are used to sample the reference level

and data level of the CCD signal, respectively. The placement

of the SHP and SHD sampling edges is determined by the setting

of the SHPPOSLOC and SHDPOSLOC Registers located at

Address 0xF0 and 0xF1, respectively. Placement of these two clock

signals is critical to achieve the best performance from the CCD.

Input Clamp

A line-rate input clamping circuit removes the CCD’s optical black

offset. This offset exists in the CCD’s shielded black reference

pixels. The AD9848/AD9849 removes this offset in the input

stage to minimize the effect of a gain change on the system black

level, usually called the “gain step.” Another advantage of remov-

ing this offset at the input stage is to maximize system headroom.

Some area CCDs have large black level offset voltages that can

significantly reduce the available headroom in the internal circuitry

when higher VGA gain settings are used, if not corrected after

the input stage.

Horizontal timing examples are shown on the last page of the

Applications Information section. It is recommended that the

CLPDM pulse be used during valid CCD dark pixels. CLPDM

may be used during the optical black pixels, either together with

CLPOB or separately. The CLPDM pulse should be a minimum

of four pixels wide.

POWER-UP PROCEDURE

VDD

(INPUT)

SERIAL

WRITES

(OUTPUT)

1 H

ODD FIELD

EVEN FIELD

...

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS

UPDATED AT VD/HD EDGE

H1/H3, RG

H2/H4

tPWR

CLI

(INPUT)

(OUTPUT)

...

Figure 14. Recommended Power-Up Sequence

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