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AD9848AKST 数据表(PDF) 29 Page - Analog Devices

部件名 AD9848AKST
功能描述  CCD Signal Processors with Integrated Timing Driver
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9848AKST 数据表(HTML) 29 Page - Analog Devices

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REV. A
AD9848/AD9849
–29–
Driving the CLI Input
The AD9848/AD9849’s master clock input (CLI) may be used in
two different configurations, depending on the application.
Figure 23a shows a typical dc-coupled input from the master clock
source. When the dc-coupled technique is used, the master clock
signal should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac-coupling capacitor may be used between
the clock source and the CLI input. In this configuration, the
CLI input will self-bias to the proper dc voltage level of approxi-
mately 1.4 V. When the ac-coupled technique is used, the
master clock signal can be as low as
±500 mV in amplitude.
17
CCD IMAGER
SIGNAL
OUT
18
13
14
20
29
H2
RG
H3
H4
H1
H2
H1
RG
AD9848/AD9849
CCDIN
Figure 22a. CCD Connections (2 H-Clock)
3V
DIGITAL
SUPPLY
SERIAL
INTERFACE
3
CCD
SIGNAL
CLOCK
INPUTS
6
0.1 F
36
35
34
33
32
31
30
29
28
27
26
25
3V
DRIVER
SUPPLY
13 14 15 16
CLOCK
INPUT
17 18 19 20 21 22 23 24
1
2
RG DRIVER
SUPPLY
3
H DRIVER
SUPPLY
4
5
6
7
8
9
10
11
3V
ANALOG
SUPPLY
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
SL
REFT
REFB
CMLEVEL
0.1 F
AVSS3
AVDD3
BYP3
D2
D3
1 F
D4
D5
D6
DVSS3
1 F
DVDD3
D7
D8
D9
D10
CCDIN
BYP2
BYP1
AVDD2
AD9849
(MSB) D11
AVSS2
3V
ANALOG
SUPPLY
0.1 F
3V
ANALOG
SUPPLY
DATA
OUTPUTS
12
0.1 F 0.1 F 0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
HIGH SPEED
CLOCKS
5
Figure 21. Recommend Circuit Configuration for External Mode



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