AD9848AKST datasheet(28/32 Pages) AD

28 / 32 page

REV. A

AD9848/AD9849

–28–

Variable Gain Amplifier

The VGA stage provides a gain range of 2 dB to 36 dB, program-

mable with 10-bit resolution through the serial digital interface.

Combined with 4 dB from the PxGA stage, the total gain range for

the AD9848/AD9849 is 6 dB to 40 dB. The minimum gain of 6 dB

is needed to match a 1 V input signal with the ADC full-scale

range of 2 V. When compared to 1 V full-scale systems (such as

ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.

The VGA gain curve is divided into two separate regions. When

the VGA Gain Register code is between 0 and 511, the curve follows

a (1 + x)/(1 – x) shape, which is similar to a “linear-in-dB”

characteristic. From code 512 to code 1023, the curve follows a

“linear-in-dB” shape. The exact VGA gain can be calculated for

any Gain Register value by using the following two equations:

Code Range

Gain Equation (dB)

0–511

Gain = 20 log10 ([658 + code]/[658 – code]) – 0.4

512–1023

Gain = (0.0354)(code) – 0.04

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 20. VGA Gain Curve (Gain from PxGA Not Included)

Optical Black Clamp

The optical black clamp loop removes residual offsets in the signal

chain to track low frequency variations in the CCD’s black level.

During the optical black (shielded) pixel interval on each line,

the ADC output is compared with a fixed black level reference,

selected by the user in the Clamp Level Register. The value can

be programmed between 0 LSB and 63.75 LSB on the AD9848

and between 0 LSB and 255 LSB on the AD9849. The clamp

level can be programmed with 8-bit resolution. The resulting

error signal is filtered to reduce noise, and the correction value is

applied to the ADC input through a D/A converter. Normally,

the optical black clamp loop is turned on once per horizontal line,

but this loop can be updated more slowly to suit a particular

application. If external digital clamping is used during the post

processing, the AD9848/AD9849 optical black clamping may be

disabled using Bit D2 in the OPRMODE Register. When the

loop is disabled, the Clamp Level Register may still be used to

provide programmable offset adjustment.

The CLPOB pulse should be placed during the CCD’s optical

black pixels. It is recommended that the CLPOB pulse duration be

at least 20 pixels wide to minimize clamp noise. Shorter pulse-

widths may be used, but clamp noise may increase, and the

ability to track low frequency variations in the black level will be

reduced. See the section on Horizontal Clamping and Blanking and

also the Applications Information section for timing examples.

A/D Converter

The AD9848/AD9849 uses high performance 10-bit/12-bit

ADC architecture, optimized for high speed and low power.

Differential Nonlinearity (DNL) performance is typically better

than 0.5 LSB. The ADC uses a 2 V input range. Better noise

performance results from using a larger ADC full-scale range.

See TPC 1 to TPC 4 for typical linearity and noise performance

plots for the AD9848/AD9849.

APPLICATIONS INFORMATION

External Circuit Configuration

The AD9848/AD9849 recommended circuit configuration for

External Mode is shown in Figure 21. All signals should be

carefully routed on the PCB to maintain low noise performance. The

CCD output signal should be connected to Pin 29 through a

0.1

µF capacitor. The CCD timing signals H1–H4 and RG should

be routed directly to the CCD with minimum trace lengths, as

shown in Figures 22a and 22b. The digital outputs and clock

inputs are located on Pins 1–12 and Pins 36–48 and should be

connected to the digital ASIC, away from the analog and CCD

clock signals. The CLI signal from the ASIC may be routed

under the package to Pin 23. This will help separate the CLI

signal from the H1–H4 and RG signal routing.

Grounding and Decoupling Recommendations

As shown in Figure 21, a single ground plane is recommended

for the AD9848/AD9849. This ground plane should be as con-

tinuous as possible, particularly around Pins 25–35. This will

ensure that all analog decoupling capacitors provide the lowest

possible impedance path between the power and bypass pins

and their respective ground pins. All decoupling capacitors

should be located as close as possible to the package pins. Plac-

ing series resistors close to the digital output pins (Pins 1–12,

47–48) may help reduce digital code transition noise. If the

digital outputs must drive a load larger than 20 pF, buffering is

recommended to minimize additional noise.

Power supply decoupling is very important for low noise performance.

Figure 21 shows the local high frequency decoupling capacitors,

but additional capacitance is recommended for lower frequencies.

Additional capacitors and ferrite beads can further reduce noise.

AD9848AKST 数据表(PDF) 28 Page - Analog Devices

AD9848AKST 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载