Advanced Clock Drivers Devices

Freescale Semiconductor

7

MPC9446

Figure 7. Output Transition Time Test Reference

Figure 11. Output Duty Cycle (DC)

Figure 12. Cycle-to-Cycle Jitter

Pulse

Generator

Z = 50

Ω

MPC9446 DUT

2.4

1.8V

0.55

0.6V

GND

GND

CCLK

Qx

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any two similar delay paths

within a single device.

GND

GND

GND

GND

CCLK

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage.

GND

The variation in cycle time of a signal between adjacent

cycles, over a random sample of adjacent cycle pairs.