MPC9446

Rev. 3, 08/2005

Freescale Semiconductor

Technical Data

© Freescale Semiconductor, Inc., 2005. All rights reserved.

2.5 V and 3.3 V LVCMOS Clock

Fanout Buffer

The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer

designed for low-voltage mid-range to high-performance telecom, networking

and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are

supported for mixed-voltage applications. The MPC9446 offers 10 low-skew

outputs and 2 selectable inputs for clock redundancy. The outputs are

configurable and support 1:1 and 1:2 output to input frequency ratios. The

MPC9446 is specified for the extended temperature range of –40

°C to 85°C.

Features

•

Configurable 10 outputs LVCMOS clock distribution buffer

•

Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply

•

Wide range output clock frequency up to 250 MHz

•

Designed for mid-range to high-performance telecom, networking

and computer applications

•

Supports applications requiring clock redundancy

•

Maximum output skew of 200 ps (150 ps within one bank)

•

Selectable output configurations per output bank

•

Tristable outputs

•

32-lead LQFP package

•

32-lead Pb-free package available

•

Ambient operating temperature range of –40 to 85

°C

Functional Description

The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and

retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are

available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three

output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose be-

tween division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three

output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Assert-

ing MR/OE will enable the outputs.

All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated

50

Ω transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible in-

puts. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

MPC9446

LOW VOLTAGE SINGLE OR

DUAL SUPPLY 2.5 V AND 3.3 V

LVCMOS CLOCK

DISTRIBUTION BUFFER