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IO130PDB3V2 数据表(PDF) 37 Page - Microsemi Corporation

部件名 IO130PDB3V2
功能描述  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

IO130PDB3V2 数据表(HTML) 37 Page - Microsemi Corporation

Back Button IO130PDB3V2 Datasheet HTML 33Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 34Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 35Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 36Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 37Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 38Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 39Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 40Page - Microsemi Corporation IO130PDB3V2 Datasheet HTML 41Page - Microsemi Corporation Next Button
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Military ProASIC3/EL Low Power Flash FPGAs
Revision 3
2-23
Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example)
D
CLK
Q
D
CLK
Q
10% VCCI
tZL
Vtrip
50%
tHZ
90% VCCI
tZH
Vtrip
50%
50%
tLZ
50%
EOUT
PAD
D
E
50%
tEOUT (R)
50%
tEOUT (F)
PAD
DOUT
EOUT
D
I/O Interface
E
tEOUT
tZLS
Vtrip
50%
tZHS
Vtrip
50%
EOUT
PAD
D
E
50%
50%
tEOUT (R)
tEOUT (F)
50%
VCC
VCC
VCC
VCCI
VCC
VCC
VCC
VOH
VOL
VOL
tZL, tZH, tHZ, tLZ, tZLS, tZHS
tEOUT = MAX(tEOUT(r), tEOUT(f))



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