IO130PDB3V2 datasheet(17/212 Pages) MICROSEMI

部件名	IO130PDB3V2

功能描述	Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

PDF	212 Pages

Scroll/Zoom	100%

制造商	MICROSEMI [Microsemi Corporation]

网页	http://www.microsemi.com

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-3

Note:

HTR time is the period during which you would not expect a verify failure due to flash cell leakage.

Figure 2-1 • High-Temperature Data Retention (HTR)

Table 2-3 •

Overshoot and Undershoot Limits1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2

Maximum Overshoot/

Undershoot (125°C)2

2.7 V or less

10%

0.72 V

0.82 V

3 V

10%

0.72 V

0.82 V

3.3 V

10%

0.69 V

0.79 V

3.6 V

10%

N/A

Notes:

1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

2. This table does not provide PCI overshoot/undershoot limits.

100

110

100 105 110 115 120 125 130 135 140 145 150

Temperature (ºC)

Tj (°C)

HTR

Lifetime

(yrs)

102.7

43.8

100

20.0

105

15.6

110

12.3

115

9.7

120

7.7

125

6.2

130

5.0

135

4.0

140

3.3

145

2.7

150

2.2

IO130PDB3V2 数据表(PDF) 17 Page - Microsemi Corporation

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