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IO130PDB3V2 数据表(PDF) 47 Page - Microsemi Corporation

部件名 IO130PDB3V2
功能描述  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

IO130PDB3V2 数据表(HTML) 47 Page - Microsemi Corporation

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Military ProASIC3/EL Low Power Flash FPGAs
Revision 3
2-33
Table 2-36 • I/O Output Buffer Maximum Resistances 1
Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only
Standard
Drive Strength
RPULL-DOWN
(
) 2
RPULL-UP
(
) 3
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range
100 µA
Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
1.8 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec



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