REV. A

AD7709

–13–

NOISE PERFORMANCE

Tables II and III show the output rms noise and output peak-to-

peak resolution in bits (rounded to the nearest 0.5 LSB) for a

selection of output update rates. The numbers are typical and

generated at a differential input voltage of 0 V. The output update

rate is selected via the SF7–SF0 bits in the Filter Register. It is

important to note that the peak-to-peak resolution figures

represent the resolution for which there will be no code flicker

within a six-sigma limit. The output noise comes from two sources.

The first is the electrical noise in the semiconductor devices

(device noise) used in the implementation of the modulator.

Second, when the analog input is converted into the digital

domain, quantization noise is added. The device noise is at a low

DIN

ADC STATUS REGISTER

(8 BITS)

CONFIGURATION REGISTER

(24 BITS)

FILTER REGISTER

(8 BITS)

ADC DATA REGISTER

(16 BITS)

REGISTER

SELECT

DECODER

DOUT

DOUT

DOUT

DOUT

DOUT

DIN

DIN

WEN R/W STBY OSCPD 0 0 A1 A0

Figure 9. On-Chip Registers

level and is independent of frequency. The quantization noise starts

at an even lower level but rises rapidly with increasing frequency

to become the dominant noise source. The numbers in the tables

are given for the bipolar input ranges. For the unipolar ranges,

the rms noise numbers will be the same as the bipolar range, but

the peak-to-peak resolution is now based on half the signal range,

which effectively means losing 1 bit of resolution.

ON-CHIP REGISTERS

The AD7709 is controlled and configured via a number of on-chip

registers, as shown in Figure 9 and described in more detail in the

following pages. In the following descriptions, set implies a Logic 1

state and cleared implies a Logic 0 state, unless otherwise stated.

Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise in

V)

SF

Data Update

Input Range

Word

Rate (Hz)

20 mV

40 mV

80 mV

160 mV

320 mV

640 mV

1.28 V

2.56 V

13

105.3

1.50

1.50

1.60

1.75

3.50

4.50

6.70

11.75

69

19.79

0.60

0.65

0.65

0.65

0.65

0.95

1.40

2.30

255

5.35

0.35

0.35

0.37

0.37

0.37

0.51

0.82

1.25

Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709 (Peak-to-Peak Resolution in Bits)

SF

Data Update

Input Range

Word

Rate (Hz)

20 mV

40 mV

80 mV

160 mV

320 mV

640 mV

1.28 V

2.56 V

13

105.3

12

13

14

15

15

15.5

16

16

69

19.79

13

14

15

16

16

16

16

16

255

5.35

14

15

16

16

16

16

16

16