AD7709 datasheet(21/32 Pages) AD

21 / 32 page

REV. A

AD7709

–21–

AD7709-to-68HC11 Interface

Figure 11 shows an interface between the AD7709 and the

68HC11 microcontroller. The diagram shows the minimum

(3-wire) interface with

CS on the AD7709 hardwired low. In this

scheme, the RDY bit of the Status Register is monitored to

determine when the Data Register is updated. An alternative

scheme, which increases the number of interface lines to four, is to

monitor the

RDY output line from the AD7709. The monitoring

of the

RDY line can be done in two ways. First, RDY can be

connected to one of the 68HC11 port bits (such as PC0), which

is configured as an input. This port bit is then polled to determine

the status of

RDY. The second scheme is to use an interrupt

driven system, in which case the

RDY output is connected to

the IRQ input of the 68HC11. For interfaces that require

control of the

CS input on the AD7709, one of the port bits of the

68HC11 (such as PC1), which is configured as an output, can

be used to drive the

CS input.

The 68HC11 is configured in the master mode with its CPOL

bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the

68HC11 is configured like this, its SCLK line idles high between

data transfers. The AD7709 is not capable of full-duplex opera-

tion. If the AD7709 is configured for a write operation, no data

appears on the DOUT lines even when the SCLK input is active.

Similarly, if the AD7709 is configured for a read operation, data

presented to the part on the DIN line is ignored even when

SCLK is active.

68HC11

VDD

AD7709

SCK

MISO

MOSI

RESET

DOUT

DIN

SCLK

VDD

Figure 11. AD7709-to-68HC11 Interface

AD7709-to-8051 Interface

An interface circuit between the AD7709 and the 8XC51 microcon-

troller is shown in Figure 12. The diagram shows the minimum

number of interface connections with

CS on the AD7709 hard-

wired low. In the case of the 8XC51 interface, the minimum

number of interconnects is just two. In this scheme, the RDY

bit of the Status Register is monitored to determine when the

Data Register is updated. The alternative scheme, which increases

the number of interface lines to three, is to monitor the

RDY output

line from the AD7709. The monitoring of the

RDY line can be

done in two ways. First,

RDY can be connected to one of the

8XC51 port bits (such as P1.0) which is configured as an input.

This port bit is then polled to determine the status of

RDY.

8XC51

VDD

AD7709

P3.0

P3.1

RESET

DIN

SCLK

DOUT

VDD

10k

Figure 12. AD7709-to-8XC51 Interface

The second scheme is to use an interrupt-driven system, in which

case the

RDY output is connected to the INT1 input of the

8XC51. For interfaces that require control of the

CS input on

the AD7709, one of the port bits of the 8XC51 (such as P1.1),

which is configured as an output, can be used to drive the

input. The 8XC51 is configured in its Mode 0 serial interface

mode. Its serial interface contains a single data line. As a result,

the DOUT and DIN pins of the AD7709 should be connected

together with a 10 k

W pull-up resistor. The serial clock on the

8XC51 idles high between data transfers. The 8XC51 outputs

the LSB first in a write operation, while the AD7709 expects the

MSB first so the data to be transmitted has to be rearranged

before being written to the output serial register. Similarly, the

AD7709 outputs the MSB first during a read operation while

the 8XC51 expects the LSB first. Therefore, the data read into

the serial buffer needs to be rearranged before the correct data

word from the AD7709 is available in the accumulator.

ADSP-2103/

ADSP-2105

VDD

AD7709

RFS

SCLK

RESET

DOUT

DIN

SCLK

TFS

Figure 13. AD7709-to-ADSP-2103/ADSP-2105 Interface

AD7709-to-ADSP-2103/ADSP-2105 Interface

Figure 13 shows an interface between the AD7709 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface shown,

the RDY bit of the Status Register is again monitored to

determine when the Data Register is updated. The alternative

scheme is to use an interrupt-driven system, in which case the

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