REV. A

AD7709

–18–

Table VIII. Filter Register Bit Designations

Table IX. Update Rate vs. SF WORD

SF (Dec)

SF (Hex)

13

0D

105.3

9.52

69

45

19.79

50.34

255

FF

5.35

186.77

Table VII. Configuration Register Bit Designations (continued)

Bit

Bit

Location

Name

Description

CONFIG3

UNI

Unipolar/Bipolar Operation Selection Bit.

Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding

i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a

code of FFFFh.

Cleared by the user to enable pseudo-bipolar operation. The device uses offset binary coding, i.e., a nega-

tive full-scale differential input will result in a code of 0000h, a 0 differential input will generate a code of

8000h, while a positive full-scale differential input will result in a code of FFFFh.

CONFIG2

RN2

This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below.

CONFIG1

RN1

This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below.

CONFIG0

RN0

This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below.

Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h)

The Filter Register is an 8-bit register from which data can be

read or to which data can be written. This register determines

the amount of averaging performed by the sinc filter. Table VIII

outlines the bit designations for the Filter Register. FR7 through

FR0 indicate the bit location, FR denoting the bits are in the

Filter Register. FR7 denotes the first bit of the data stream. The

number in brackets indicates the power-on/reset default status

of that bit. The number in this register is used to set the decima-

tion factor and thus the output update rate for the ADC. The

Filter Register cannot be written to by the user while the ADC

is active. The update rate is calculated as follows:

f

SF

f

ADC

MOD

=¥ ¥ ¥

1

3

1

8

where:

SF is the decimal value written to the SF Register.

The allowable range for SF is 13dec to 255dec. Examples of SF

are shown in Table IX. It should also be noted that the ADC

input channel is chopped to minimize offset errors. This means

that the time for a single conversion or the time to the first con-

version result is 2

ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset =

0000h)

The conversion result is stored in the ADC Data Register (DATA).

This register is 16-bits wide. This is a read-only register. On

completion of a read from this register, the RDY bit in the

Status Register is cleared.

7

R

F6

R

F5

R

F4

R

F3

R

F2

R

F1

R

F0

R

F

)

0

(

7

F

S)

1

(

6

F

S)

0

(

5

F

S)

0

(

4

F

S)

0

(

3

F

S)

1

(

2

F

S)

0

(

1

F

S)

1

(

0

F

S

RN2

RN1

RN0

00

0

±20 mV

00

1

±40 mV

01

0

±80 mV

01

1

±160 mV

10

0

±320 mV

10

1

±640 mV

11

0

±1.28 V

11

1

±2.56 V