REV. A

AD7709

–16–

Table VII. Configuration Register Bit Designations

Bit

Bit

Location

Name

Description

CONFIG23

PSW2

Power Switch 2 Control Bit.

Set by user to enable power switch SW2/P2 to PWRGND.

Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches

are open.

CONFIG22

PSW1

Power Switch 1 Control Bit.

Set by user to enable power switch SW1/P1 to PWRGND.

Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches

are open.

CONFIG21

I3EN1

IEXC3 Current Source Enable Bit

CONFIG20

I3EN0

IEXC3 Current Source Enable Bit

CONFIG19

I2EN1

IEXC2 Current Source Enable Bit

CONFIG18

I2EN0

IEXC2 Current Source Enable Bit

CONFIG17

I1EN1

IEXC1 Current Source Enable Bit

Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H)

The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to

select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations

for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register.

CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. A

write to the Configuration Register has immediate effect and does not reset the ADC. Therefore, if a current source is switched

while the ADC is converting, the user will have to wait for the full settling time of the sinc

This equates to three outputs.

7

G

I

F

N

O

C7

G

I

F

N

O

C

7

G

I

F

N

O

C

7

G

I

F

N

O

C7

G

I

F

N

O

C6

G

I

F

N

O

C6

G

I

F

N

O

C

6

G

I

F

N

O

C

6

G

I

F

N

O

C6

G

I

F

N

O

C5

G

I

F

N

O

C5

G

I

F

N

O

C

5

G

I

F

N

O

C

5

G

I

F

N

O

C5

G

I

F

N

O

C4

G

I

F

N

O

C4

G

I

F

N

O

C

4

G

I

F

N

O

C

4

G

I

F

N

O

C4

G

I

F

N

O

C3

G

I

F

N

O

C3

G

I

F

N

O

C

3

G

I

F

N

O

C

3

G

I

F

N

O

C3

G

I

F

N

O

C2

G

I

F

N

O

C2

G

I

F

N

O

C

2

G

I

F

N

O

C

2

G

I

F

N

O

C2

G

I

F

N

O

C1

G

I

F

N

O

C1

G

I

F

N

O

C

1

G

I

F

N

O

C

1

G

I

F

N

O

C1

G

I

F

N

O

C0

G

I

F

N

O

C0

G

I

F

N

O

C

0

G

I

F

N

O

C

0

G

I

F

N

O

C0

G

I

F

N

O

C

)

0

(

L

E

S

F

E

R)

0

(

L

E

S

F

E

R

)

0

(

L

E

S

F

E

R

)

0

(

L

E

S

F

E

R)

0

(

L

E

S

F

E

R)

0

(

2

H

C)

0

(

2

H

C

)

0

(

2

H

C

)

0

(

2

H

C)

0

(

2

H

C)

0

(

1

H

C)

0

(

1

H

C

)

0

(

1

H

C

)

0

(

1

H

C)

0

(

1

H

C)

0

(

0

H

C)

0

(

0

H

C

)

0

(

0

H

C

)

0

(

0

H

C)

0

(

0

H

C)

0

(

I

N

U)

1

(

2

N

R)

1

(

1

N

R)

1

(

0

N

R

3

2

G

I

F

N

O

C3

2

G

I

F

N

O

C

3

2

G

I

F

N

O

C

3

2

G

I

F

N

O

C3

2

G

I

F

N

O

C2

2

G

I

F

N

O

C2

2

G

I

F

N

O

C

2

2

G

I

F

N

O

C

2

2

G

I

F

N

O

C2

2

G

I

F

N

O

C1

2

G

I

F

N

O

C1

2

G

I

F

N

O

C

1

2

G

I

F

N

O

C

1

2

G

I

F

N

O

C1

2

G

I

F

N

O

C0

2

G

I

F

N

O

C0

2

G

I

F

N

O

C

0

2

G

I

F

N

O

C

0

2

G

I

F

N

O

C0

2

G

I

F

N

O

C9

1

G

I

F

N

O

C9

1

G

I

F

N

O

C

9

1

G

I

F

N

O

C

9

1

G

I

F

N

O

C9

1

G

I

F

N

O

C8

1

G

I

F

N

O

C8

1

G

I

F

N

O

C

8

1

G

I

F

N

O

C

8

1

G

I

F

N

O

C8

1

G

I

F

N

O

C7

1

G

I

F

N

O

C7

1

G

I

F

N

O

C

7

1

G

I

F

N

O

C

7

1

G

I

F

N

O

C7

1

G

I

F

N

O

C6

1

G

I

F

N

O

C6

1

G

I

F

N

O

C

6

1

G

I

F

N

O

C

6

1

G

I

F

N

O

C6

1

G

I

F

N

O

C

)

0

(

2

W

S

P)

0

(

2

W

S

P

)

0

(

2

W

S

P

)

0

(

2

W

S

P)

0

(

2

W

S

P)

0

(

1

W

S

P)

0

(

1

W

S

P

)

0

(

1

W

S

P

)

0

(

1

W

S

P)

0

(

1

W

S

P)

0

(

1

N

E

3

I)

0

(

1

N

E

3

I

)

0

(

1

N

E

3

I

)

0

(

1

N

E

3

I)

0

(

1

N

E

3

I)

0

(

0

N

E

3

I)

0

(

0

N

E

3

I

)

0

(

0

N

E

3

I

)

0

(

0

N

E

3

I)

0

(

0

N

E

3

I)

0

(

1

N

E

2

I)

0

(

1

N

E

2

I

)

0

(

1

N

E

2

I

)

0

(

1

N

E

2

I)

0

(

1

N

E

2

I)

0

(

0

N

E

2

I)

0

(

0

N

E

2

I

)

0

(

0

N

E

2

I

)

0

(

0

N

E

2

I)

0

(

0

N

E

2

I)

0

(

1

N

E

1

I)

0

(

1

N

E

1

I

)

0

(

1

N

E

1

I

)

0

(

1

N

E

1

I)

0

(

1

N

E

1

I)

0

(

0

N

E

1

I)

0

(

0

N

E

1

I

)

0

(

0

N

E

1

I

)

0

(

0

N

E

1

I)

0

(

0

N

E

1

I

I2EN1

I2EN0

Function

00

IEXC2 Current Source OFF

01

IEXC2 Current Source Routed to the IOUT1 Pin

10

IEXC2 Current Source Routed to the IOUT2 Pin

11

Reserved

I3EN1

I3EN0

Function

00

IEXC3 Current Source OFF

01

IEXC3 Current Source Routed to the IOUT1 Pin

10

IEXC3 Current Source Routed to the IOUT2 Pin

11

Reserved

5

1

G

I

F

N

O

C4

1

G

I

F

N

O

C3

1

G

I

F

N

O

C2

1

G

I

F

N

O

C1

1

G

I

F

N

O

C0

1

G

I

F

N

O

C9

G

I

F

N

O

C8

G

I

F

N

O

C

)

0

(

G

I

D

4

P)

0

(

G

I

D

3

P)

0

(

N

E

2

P)

0

(

N

E

1

P)

0

(

T

A

D

4

P)

0

(

T

A

D

3

P)

0

(

T

A

D

2

P)

0

(

T

A

D

1

P