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DSPIC30F2011AT-30E/PF 数据表(PDF) 20 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF 数据表(HTML) 20 Page - Microchip Technology |
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20 / 228 page  dsPIC30F6011/6012/6013/6014 DS70117F-page 18 © 2006 Microchip Technology Inc. 2.3 Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The fol- lowing instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2. DIV.sd - 32/16 signed divide 3. DIV.ud - 32/16 unsigned divide 4. DIV.sw - 16/16 signed divide 5. DIV.uw - 16/16 unsigned divide The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration. The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the REPEAT instruc- tion as shown in Table 2-1 (REPEAT will execute the tar- get instruction {operand value + 1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. TABLE 2-1: DIVIDE INSTRUCTIONS Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Instruction Function DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm + 1:Wm/Wn → W0; Rem → W1 DIV.sw Signed divide: Wm/Wn → W0; Rem → W1 DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1 |
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