DSPIC30F2011AT-30ESLASHPF datasheet(97/228 Pages) MICROCHIP

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DS70117F-page 95

dsPIC30F6011/6012/6013/6014

15.0

I2C MODULE

The Inter-Integrated Circuit (I2CTM) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

This module offers the following key features:

•I2C interface supporting both master and slave

operation.

•I2C Slave mode supports 7 and 10-bit address.

•I2C Master mode supports 7 and 10-bit address.

•I2C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

•I2C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

15.1

Operating Function Description

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

Thus, the I2C module can operate either as a slave or

a master on an I2C bus.

15.1.1

VARIOUS I2C MODES

The following types of I2C operation are supported:

•I2C slave operation with 7-bit address

•I2C slave operation with 10-bit address

•I2C master operation with 7 or 10-bit address

See the I2C programmer’s model in Figure 15-1.

15.1.2

PIN CONFIGURATION IN I2C MODE

I2C has a 2-pin interface: the SCL pin is clock and the

SDA pin is data.

15.1.3

I2C REGISTERS

I2CCON and I2CSTAT are control and status registers,

respectively. The I2CCON register is readable and writ-

able. The lower 6 bits of I2CSTAT are read only. The

remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer as shown in Figure 15-1.

I2CTRN is the transmit register to which bytes are

written during a transmit operation, as shown in

Figure 15-2.

The I2CADD register holds the slave address. A status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator (BRG)

reload value.

In receive operations, I2CRSR and I2CRCV together

form a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and

interrupt

pulse

generated.

During

transmission, the I2CTRN is not double-buffered.

FIGURE 15-1:

PROGRAMMER’S MODEL

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note:

Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit address.

Bit 7

Bit 0

I2CRCV (8 bits)

Bit 7

Bit 0

I2CTRN (8 bits)

Bit 8

Bit 0

I2CBRG (9 bits)

Bit 15

Bit 0

I2CCON (16 bits)

Bit 15

Bit 0

I2CSTAT (16 bits)

Bit 9

Bit 0

I2CADD (10 bits)

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