AD-DPGIOZ datasheet(7/61 Pages) AD

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Data Sheet

AD9961/AD9963

Rev. A | Page 7 of 60

Table 5. Digital Logic Level Specifications

Parameter

Conditions

Min

Typ

Max

Unit

CMOS INPUT LOGIC LEVEL

IN Logic High

DRVDD = 1.8 V

1.2

IN Logic High

DRVDD = 2.5 V

1.7

IN Logic High

DRVDD = 3.3 V

2.0

IN Logic Low

DRVDD = 1.8 V

0.5

IN Logic Low

DRVDD = 2.5 V

0.7

IN Logic Low

DRVDD = 3.3 V

0.8

CMOS OUTPUT LOGIC LEVEL

OUT Logic High

DRVDD = 1.8 V

1.35

OUT Logic High

DRVDD = 2.5 V

2.05

OUT Logic High

DRVDD = 3.3 V

2.4

OUT Logic Low

DRVDD = 1.8 V

0.4

OUT Logic Low

DRVDD = 2.5 V

0.4

OUT Logic Low

DRVDD = 3.3 V

0.4

DAC CLOCK INPUT

Differential Peak-to-Peak Voltage

200

400

CLK33V

mV p-p diff

Duty Cycle

Slew Rate

0.1

V/ns

DIRECT CLOCKING

Clock Rate

CLKP/CLKN inputs

0.1

200

MHz

DLL ENABLED

Clock Rate

DLL delay line output

100

310

MHz

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate

MHz

Minimum Pulse Width High (t

HIGH)

Minimum Pulse Width Low (t

LOW)

Setup Time, SDIO (Data In) to SCLK (t

DS)

5.0

Hold Time, SDI to SCLK (t

DH)

5.0

Data Valid, SDIO (Data Out) to SCLK (t

DV)

5.0

Setup Time, CS to SCLK (tS)

5.0

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