AD-DPGIOZ datasheet(21/61 Pages) AD

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Data Sheet

AD9961/AD9963

Rev. A | Page 21 of 60

When LSB first is set by Register 0x00, Bit 2 and Register 0x00,

Bit 6, it takes effect immediately. In multibyte transfers,

subsequent bytes reflect any changes in the serial port

configuration. To avoid problems reconfiguring the serial port

operation, any data written to 0x00 must be mirrored (the eight

bits should read the same, forward or backward). Mirroring the

data makes it irrelevant whether LSB first or MSB first is in

effect. As an example of this mirroring, the default setting for

Ending Transfers

When the transfer is 1, 2, or 3 bytes, the data transfer ends after

the required number of clock cycles have been received. CS can

be raised after each sequence of eight bits to stall the bus (except

after the last byte, where it ends the cycle). When the bus is

stalled, the serial transfer resumes when CS is lowered. Raising

CS on a non byte boundary resets the serial control port.

The AD9961/AD9963 serial control port register addresses

decrement from the register address just written toward 0x00

for multibyte I/O operations if the MSB first mode is active

(default). If the LSB first mode is active, the register address of

the serial control port increments from the address just written

toward 0xFF for multibyte I/O operations.

Streaming mode transfers always terminate when CS is raised.

Streaming mode transfers also terminate whenever the address

reaches 0xFF. Note that unused addresses are not skipped

during multibyte I/O operations. To avoid unpredictable device

behavior, do not write to reserved registers.

Table 11. Streaming Mode (No Addresses Are Skipped)

Write Mode

Address Direction

Stop Sequence

LSB First

Increment

0xFD, 0xFE, 0xFF, stop

MSB First

Decrement

0x01, 0x00, 0xFF, stop

SUB SERIAL INTERFACE COMMUNICATIONS

The AD9963/AD9961 have two registers that require a different

communication sequence. These registers are 0x0F and 0x10.

The write sequence for these two registers requires a write to

write to Register 0xFF. The write takes effect when the write to

For example, to enable the RXCML pin output buffer, the

Write 0x03 into Register 0x05. This addresses both of the

Rx ADCs.

Write 0x02 into Register 0x0F. This sets the RXCML

enable bit.

Write 0x01 into Register 0xFF. This updates the internal

Write 0x00 into Register 0x05. This returns the SPI to the

normal addressing mode.

An example of updating Register 0x10 is given in the ADC

Digital Offset Adjustment section.

Table 12. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I15

I14

I13

I12

I11

I10

R/W

SCLK DON’T CARE

SDIO

A12

R/W

A11 A10 A9

D7 D6

DON’T CARE

16-BIT INSTRUCTION HEADER

Figure 34. Serial Control Port Access—MSB First, 16-Bit Instruction, 2-Byte Data

DON’T CARE

N0A12

A11

A10

A9A8A7A6A5

D4D3

D2D1D0

DON’T CARE

R/W

tDS

tDH

tHIGH

tLOW

tCLK

SCLK

SDIO

Figure 35. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

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