AD-DPGIOZ datasheet(22/61 Pages) AD

22 / 61 page

AD9961/AD9963

Data Sheet

Rev. A | Page 22 of 60

DATA BIT N – 1

DATA BIT N

SCLK

SDIO

SDO

tDV

Figure 36. Timing Diagram for Serial Control Port Register Read

SCLK DON’T CARE

DON’T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON’T CARE

A9 A10 A11 A12

R/W

Figure 37. Serial Control Port Access—LSB First, 16-Bit Instruction, Two Bytes Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 38. Serial Control Port Timing—Write

Table 13. Serial Control Port Timing

Parameter

Timing (Min, ns)

Description

tDS

5.0

Setup time between data and rising edge of SCLK.

tDH

5.0

Hold time between data and rising edge of SCLK.

tCLK

20.0

Period of the clock.

5.0

Setup time between CS falling edge and SCLK rising edge (start of communication

cycle).

Setup time between SCLK rising edge and CS rising edge (end of communication

cycle).

tHIGH

Minimum period that SCLK should be in a logic high state.

tLOW

Minimum period that SCLK should be in a logic low state.

tDV

5.0

SCLK to valid SDIO and SDO (see Figure 36).

AD-DPGIOZ 数据表(PDF) 22 Page - Analog Devices

AD-DPGIOZ 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载

链接网址

AD-DPGIOZ 数据表(PDF) 22 Page - Analog Devices

AD-DPGIOZ 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表 下载

链接网址

数据表下载