REV. B

AD8381

–5–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

Description

1, 12, 19, 23, NC

No Connect

24, 43–45

2–11

DB (0:9)

Data Input

10-Bit Data Input MSB = DB (9).

13

E/O

Even/Odd Select

The active CLK edge is the rising edge when this input is held high,

and it is the falling edge when this input is held low.

Data is loaded sequentially on the rising edges of CLK when this input

is high and loaded on the falling edges when this input is low.

14

R/L

Right/Left Select

A new data loading sequence begins on the left, with Channel 0, when this

input is low, and on the right, with Channel 5, when this input is high.

15

INV

Invert

When this pin is high, the analog output voltages are above VMID.

When low, the analog output voltages are below VMID.

16

DGND

Digital Supply Return

This pin is normally connected to the analog ground plane.

17

DVCC

Digital Power Supply

Digital Power Supply.

18, 27, 31

AVCCx

Analog Power Supplies

Analog Power Supplies.

35, 42

20

STBY

Standby

When high, the internal circuits are debiased and the power

dissipation drops to a minimum.

21

BYP

Bypass

A 0.1

mF capacitor connected between this pin and AGND ensures

optimum settling time.

22, 25, 29

AGNDx

Analog Supply Returns

These pins are normally connected to the analog ground plane.

33, 37, 41

26, 28, 30,

VID5, VID4, VID3,

Analog Outputs

These pins are directly connected to the analog inputs of the LCD panel.

32, 34, 36

VID2, VID1, VID0

38

VMID

Midpoint Reference

The voltage applied between this pin and AGND sets the midpoint

reference of the analog outputs. This pin is normally connected to VCOM.

39

VREFLO

Full-Scale Reference

The voltage applied between Pins 39 and 40 sets the full-scale output voltage.

40

VREFHI

Full-Scale Reference

The voltage applied between Pins 39 and 40 sets the full-scale output voltage.

46

STSQ

Start Sequence

A new data loading sequence begins on the rising edge of CLK when

this input was high on the preceding rising edge of CLK and the E/O

input is held high.

A new data loading sequence begins on the falling edge of CLK when

this input was high on the preceding falling edge of CLK and the E/O

input is held low.

47

XFR

Data Transfer

Data is transferred to the outputs on the immediately following falling

edge of CLK when this input is high on the rising edge of CLK.

48

CLK

Clock

Clock Input.

PIN CONFIGURATION

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

VID0

AVCC0, 1

VID1

AGND1, 2

VID2

AVCC2, 3

VID3

NC

DB0

DB1

DB2

DB3

DB4

DB5

NC = NO CONNECT

DB6

DB7

DB8

DB9

AGND3, 4

VID4

AVCC4, 5

VID5

AD8381

NC

AGND5