REV. B

AD8381

–14–

LAYOUT CONSIDERATIONS

The AD8381 is a mixed-signal, high speed, very accurate

device. In order to realize its specifications, it is essential to use

a properly designed printed circuit board.

Layout and Grounding

The analog outputs and the digital inputs of the AD8381 are

pinned out on opposite sides of the package. When laying out

the circuit board, keep these sections separate from each other

to minimize crosstalk and noise and the coupling of the digital

input signals into the analog outputs.

All signal trace lengths should be made as short and direct as

possible to prevent signal degradation due to parasitic effects.

Note that digital signals should not cross or be routed near

analog signals.

It is imperative to provide a solid analog ground plane under

and around the AD8381. All of the ground pins of the part

should be connected directly to the ground plane with no extra

signal path length. For conventional operation this includes the

pins DGND, AGNDDAC, AGNDBIAS, AGND0, AGND1,2,

AGND3,4, and AGND5. The return traces for any of the

signals should be routed close to the ground pin for that section

to prevent stray signals from coupling into other ground pins.

Power Supply Bypassing

All power supply and reference pins of the AD8381 must be

properly bypassed to the analog ground plane for optimum

performance.

All analog supply pins may be connected directly to an analog

supply plane located as close to the part as possible. A 0.1

mF

chip capacitor should be placed as close to each analog supply

pin as possible and connected directly between each analog

supply pin and the analog ground plane.

A minimum of 47

mF tantalum capacitor should be placed near

the analog supply plane and connected directly between the

supply and analog ground planes.

A minimum of 10

mF tantalum capacitor should be placed near the

digital supply pin and connected directly to the analog ground

plane. A 0.1

mF chip capacitor should be connected between the

digital supply pin and the analog ground.

VREFHI, VMID, VREFLO Reference Distribution

To ensure well-matched video outputs, all AD8381s must oper-

ate from equal reference voltages.

Each reference voltage should be distributed to each AD8381

directly from the source of the reference voltage with approxi-

mately equal trace lengths.

A 0.1

mF chip capacitor should be placed as close to each refer-

ence input pin as possible and directly connected between the

reference input pin and the analog ground plane.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

VID0

VID1

AVCC0 ,1

VID2

AGND1,2

VID3

AVCC2 ,3

VID4

AGND3,4

VID5

AVCC4 ,5

AGND5

12

11

10

9

8

7

6

5

4

3

2

1

26

28

30

32

34

36

TO ANALOG GROUND PLANE

TO ANALOG SUPPLY PLANE

Figure 11.