AD8381 datasheet(2/16 Pages) AD

2 / 16 page

REV. B

–2–

AD8381–SPECIFICATIONS

(@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, VREFLO = VMID = 7 V, VREFHI = 9.5 V,

TMIN = 0 C, TMAX = 85 C, unless otherwise noted.)

Model

Conditions

Min

Typ

Max

Unit

VIDEO DC PERFORMANCE

TMIN to TMAX

VDE

DAC Code 450 to 800

–7.5

+1.0

+7.5

VCME

DAC Code 450 to 800

–3.5

+0.5

+3.5

REFERENCE INPUTS

(VREFHI – VREFLO) = 2.5 V

VMID Range

6.25

9.25

VMID Bias Current

VREFHI

VREFLO

AVCC

VREFLO

VMID – 0.5

VREFHI

VREFHI Input Resistance

to VREFLO

VREFLO Bias Current

0.01

0.07

VREFHI Input Current

125

165

VFS Range

5.75

RESOLUTION

Coding

Binary

Bits

DIGITAL INPUT CHARACTERISTICS

CLK Rise and Fall Time = 5 ns

Input Data Update Rate

NRZ

100

Ms/s

CLK to Data Setup Time: t1

0ns

CLK to STSQ Setup Time: t3

0ns

CLK to XFR Setup Time: t5

0ns

CLK to Data Hold Time: t2

5ns

CLK to STSQ Hold Time: t4

5ns

CLK to XFR Hold Time: t6

5ns

tCLK HIGH

E/O = HIGH

4.5

tCLK LOW

3.5

CIN

3pF

IIH

0.6

0.7

IIL

0.05

0.16

VIH

2.0

VIL

0.8

VTH

Threshold Voltage

1.4

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing

AVCC – VOH, VOL – AGND

1.3

CLK to VID Delay

4: t

50% of VIDx

13.5

15.5

17.5

INV to VID Delay

50% of VIDx

Output Current

Output Resistance

VIDEO OUTPUT DYNAMIC PERFORMANCE

TMIN to TMAX, VO = 5 V Step, CL = 150 pF

Data Switching Slew Rate

265

Invert Switching Slew Rate

410

Data Switching Settling Time to 1%

Data Switching Settling Time to 0.25%

Invert Switching Settling Time to 1%

Invert Switching Settling Time to 0.25%

100

CLK and Data Feedthrough

mV p-p

All-Hostile Crosstalk

Amplitude

mV p-p

Glitch Duration

POWER SUPPLY

Supply Rejection (VDE)

AVCCx = +15.5 V

± 1 V

0.6

mV/V

DVCC, Operating Range

5.5

DVCC, Quiescent Current

AVCC, Operating Range

918

Total AVCC Quiescent Current

STBY AVCC Current

STBY = H

1.8

STBY DVCC Current

STBY = H

0.03

0.1

OPERATING TEMPERATURE RANGE

∞C

NOTES

1VDE = Differential error voltage. VCME = Common-mode error voltage. See the Theory of Operation section.

2See Figure 6 in Theory of Operation section.

3VFS = 2

¥ (VREFHI – VREFLO). See the Theory of Operation section.

4Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.

5Measured on one output as CLK is driven and STSQ and XFR are held low.

6Measured on one output as the other five are changing from 0x000 to 0x3FF for both states of INV.

Specifications subject to change without notice.

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