AD9754

–12–

REV. A

The most significant improvement in the AD9754’s distortion

and noise performance is realized using a differential output

configuration. The common-mode error sources of both

IOUTA and IOUTB can be substantially reduced by the

common-mode rejection of a transformer or differential am-

plifier. These common-mode error sources include even-order

distortion products and noise. The enhancement in distortion

performance becomes more significant as the reconstructed

waveform’s frequency content increases and/or its amplitude

decreases.

The distortion and noise performance of the AD9754 is also

slightly dependent on the analog and digital supply as well as the

5.0 V ensures maximum headroom for its internal PMOS current

sources and differential switches leading to improved distortion

distortion and noise performance also shown in Figure 13. The

noise performance of the AD9754 is affected by the digital sup-

ply (DVDD), output frequency, and increases with increasing

clock rate as shown in Figure 8. Operating the AD9754 with

low voltage logic levels between 3 V and 3.3 V will slightly

reduce the amount of on-chip digital noise.

In summary, the AD9754 achieves the optimum distortion and

noise performance under the following conditions:

(1) Differential Operation.

(2) Positive voltage swing at IOUTA and IOUTB limited to

+0.5 V.

(4) Analog Supply (AVDD) set at 5.0 V.

(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-

priate logic levels.

Note that the ac performance of the AD9754 is characterized

under the above mentioned operating conditions.

DIGITAL INPUTS

The AD9754’s digital input consists of 14 data input pins and a

clock input pin. The 14-bit parallel data inputs follow standard

positive binary coding where DB13 is the most significant bit

(MSB), and DB0 is the least significant bit (LSB). IOUTA

produces a full-scale output current when all data bits are at

Logic 1. IOUTB produces a complementary output with the

full-scale current split between the two outputs as a function of

the input code.

The digital interface is implemented using an edge-triggered

master slave latch. The DAC output is updated following the

rising edge of the clock as shown in Figure 1 and is designed to

support a clock rate as high as 125 MSPS. The clock can be

operated at any duty cycle that meets the specified latch pulse

width. The setup and hold times can also be varied within the

clock cycle as long as the specified minimum times are met,

although the location of these transition edges may affect digital

feedthrough and distortion performance. Best performance is

typically achieved when the input data transitions on the falling

edge of a 50% duty cycle clock.

The digital inputs are CMOS-compatible with logic thresholds,

(DVDD) or

±20%)

The internal digital circuitry of the AD9754 is capable of operating

over a digital supply range of 2.7 V to 5.5 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage of the TTL

proper compatibility with most TTL logic families. Figure 22

shows the equivalent digital input circuit for the data and clock

inputs. The sleep mode input is similar with the exception that

it contains an active pull-down circuit, thus ensuring that the

AD9754 remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 22. Equivalent Digital Input

Since the AD9754 is capable of being updated up to 125 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. Operating the AD9754

with reduced logic swings and a corresponding digital supply

(DVDD) will result in the lowest data feedthrough and on-chip

digital noise. The drivers of the digital data interface circuitry

should be specified to meet the minimum setup and hold times

of the AD9754 as well as its required min/max input logic level

thresholds.

Digital signal paths should be kept short and run lengths

matched to avoid propagation delay mismatch. The insertion of

a low value resistor network (i.e., 20

Ω to 100 Ω) between the

AD9754 digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs that

contribute to data feedthrough. For longer run lengths and high

data update rates, strip line techniques with proper termination

resistors should be considered to maintain “clean” digital inputs.

The external clock driver circuitry should provide the AD9754

with a low jitter clock input meeting the min/max logic levels

while providing fast edges. Fast clock edges will help minimize

any jitter that will manifest itself as phase noise on a recon-

structed waveform. Thus, the clock input should be driven by

the fastest logic family suitable for the application.

Note, that the clock input could also be driven via a sine wave,

which is centered around the digital threshold (i.e., DVDD/2)

and meets the min/max logic threshold. This will typically result

in a slight degradation in the phase noise, which becomes more

noticeable at higher sampling rates and output frequencies.

Also, at higher sampling rates, the 20% tolerance of the digital

logic threshold should be considered since it will affect the effec-

tive clock duty cycle and, subsequently, cut into the required

data setup and hold times.