AD7476BRTZ-R23 datasheet(13/24 Pages) AD

13 / 24 page

AD7476/AD7477/AD7478

Rev. F | Page 13 of 24

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,

and 8-bit, fast, micropower, single-supply ADCs. The parts can

be operated from a 2.35 V to 5.25 V supply. When operated

from either a 5 V supply or a 3 V supply, the AD7476/AD7477/

AD7478 are capable of throughput rates of 1 MSPS when

provided with a 20 MHz clock.

Each AD7476/AD7477/AD7478 provides an on-chip, track-

and-hold ADC and a serial interface housed in a tiny 6-lead

SOT-23 package, which offers considerable space-saving

advantages. The serial clock input accesses data from the part

and provides the clock source for the successive-approximation

ADC. The analog input range is 0 V to VDD. An external

reference is not required for the ADC, nor is there a reference

on-chip. The reference for the AD7476/AD7477/AD7478 is

derived from the power supply and thus provides the widest

dynamic input range.

The AD7476/AD7477/AD7478 also feature a power-down

option to save power between conversions. The power-down

feature is implemented across the standard serial interface as

described in the Modes of Operation section.

CONVERTER OPERATION

The AD7476/AD7477/AD7478 are successive-approximation

analog-to-digital converters based around a charge redistribu-

tion DAC. Figure 1 and Figure 11 show simplified schematics

of the ADC. Figure 10 shows the ADC during its acquisition

phase. SW2 is closed and SW1 is in Position A, the comparator

is held in a balanced condition, and the sampling capacitor

acquires the signal on VIN.

COMPARATOR

SAMPLING

CAPACITOR

ACQUISITION

PHASE

AGND

SW1

SW2

VIN

VDD/2

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 10. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 11), SW2 opens

and SW1 moves to Position B, causing the comparator to

become unbalanced. The control logic and the charge redistri-

bution DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. Figure 12 and Figure 13 show the ADC

transfer function.

COMPARATOR

SAMPLING

CAPACITOR

CONVERSION

PHASE

AGND

SW1

SW2

VIN

VDD/2

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 11. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7476/AD7477/AD7478 is straight

binary. For the AD7476/AD7477, designed code transitions

occur midway between successive integer LSB values, such as ½

LSB, 1½ LSB, and so on. The LSB size for the AD7476 is

VDD/4096, and the LSB size for the AD7477 is VDD/1024. The

ideal transfer characteristic for the AD7476/AD7477 is shown

in Figure 12.

For the AD7478, designed code transitions occur midway

between successive integer LSB values, such as 1 LSB, 2 LSB,

and so on. The LSB size for the AD7478 is VDD/256. The ideal

transfer characteristic for the AD7478 is shown in Figure 13.

ANALOG INPUT

111 ... 111

0.5LSB

+VDD – 1.5LSB

111 ... 110

111 ... 000

011 ... 111

000 ... 010

000 ... 001

000 ... 000

1LSB = VDD/4096 (AD7476)

1LSB = VDD/1024 (AD7477)

Figure 12. Transfer Characteristic for the AD7476/AD7477

ANALOG INPUT

111 ... 111

1LSB

+VDD – 1LSB

111 ... 110

111 ... 000

011 ... 111

000 ... 010

000 ... 001

000 ... 000

1LSB = VDD/256 (AD7478)

Figure 13. Transfer Characteristic for AD7478

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