AD7476/AD7477/AD7478

Rev. F | Page 15 of 24

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

10k

1k

100

10

SOURCE IMPEDANCE (

Ω)

Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies

–50

–90

–85

–80

–75

–70

–65

–60

–55

10k

1M

100k

INPUT FREQUENCY (Hz)

–72

–74

–76

–78

–80

–82

–84

10k

1M

100k

INPUT FREQUENCY (Hz)

Digital Input

The digital input applied to the AD7476/AD7477/AD7478 is

not limited by the maximum ratings that limit the analog input.

Instead, the digital input applied can go to 7 V and is not

example, if the AD7476/AD7477/AD7478 are operated with a

However, note that the data output on SDATA still has 3 V logic

sequencing issues are avoided. If CS or SCLK is applied before

MODES OF OPERATION

Select the mode of operation of the AD7476/AD7477/AD7478

by controlling the (logic) state of the CS signal during a

conversion. The two possible modes of operation are normal

mode and power-down mode. The point at which CS is pulled

high after the conversion has been initiated determines whether

or not the AD7476/AD7477/AD7478 enters power-down mode.

Similarly, if already in power-down, CS can control whether the

device returns to normal operation or remains in power-down.

These modes of operation are designed to provide flexible

power management options. These options can be chosen to

optimize the power dissipation/throughput rate ratio for

different application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance.

Users do not have to worry about power-up times with the

AD7476/AD7477/AD7478 remaining fully powered at all times.

Figure 19 shows the general diagram of the AD7476/AD7477/

AD7478 in normal mode.

The conversion is initiated on the falling edge of CS as de-

scribed in the

section. To ensure the part

remains fully powered up at all times,

Serial Interface

CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

of CS. If CS is brought high any time after the tenth SCLK

falling edge, but before the sixteenth SCLK falling edge, the part

remains powered up, but the conversion terminates and SDATA

goes back into three-state. Sixteen serial clock cycles are

required to complete the conversion and access the complete

conversion result. CS may idle high until the next conversion or

may idle low until CS returns high sometime prior to the next

conversion (effectively idling CS low).

Once a data transfer is complete, (SDATA has returned to three-

state), another conversion can be initiated after the quiet time,