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201998B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 20, 2013

AAT1162

12V, 1.5A Step-Down DC/DC Converter

DATA SHEET

Manufacturer

Part Number

L (μH)

Max DCR

(mΩ)

Rated DC

Current (A)

Size WxLxH

(mm)

Sumida

CDRH103RNP-2R2N

2.2

16.9

5.10

10.3x10.5x3.1

Sumida

CDR7D43MNNP-3R7NC

3.7

18.9

4.3

7.6x7.6x4.5

Coilcraft

MSS1038-382NL

3.8

13

4.25

10.2x7.7x3.8

Cooper Bussman

DR73-4R7-R

4.7

29.7

3.09

6.0x7.6x3.55

Wurth

7440530047

4.7

38

2.40

5.8x5.8x2.8

Table 2: Typical Surface Mount Inductors.

To estimate the required input capacitor size, determine

The calculated value varies with input voltage and is a

⎛⎞

· 1 -

⎝⎠

⎛⎞

- ESR

·

⎝⎠

⎛⎞

· 1 -

=

⎝⎠

1

4

1

⎛⎞

- ESR

·

⎝⎠

Always examine the ceramic capacitor DC voltage coef-

ficient characteristics when selecting the proper value.

For example, the capacitance of a 10μF, 16V, X5R ceram-

ic capacitor with 12V DC applied is actually about 8.5μF.

The maximum input capacitor RMS current is:

⎛⎞

· 1 -

⎝⎠

The input capacitor RMS ripple current varies with the

input and output voltage and will always be less than or

equal to half of the total DC load current:

⎛⎞

· 1 -

⎝⎠

1

2

RMS(MAX)

I

2

=

The term

⎛⎞

· 1 -

⎝⎠

appears in both the input voltage

ripple and input capacitor RMS current equations and is

voltage ripple and the input capacitor RMS current ripple

are a maximum at 50% duty cycle. The input capacitor

provides a low impedance loop for the edges of pulsed

current drawn by the AAT1162. Low ESR/ESL X7R and

X5R ceramic capacitors are ideal for this function. To

minimize stray inductance, the capacitor should be

placed as closely as possible to the IC. This keeps the

high frequency content of the input current localized,

minimizing EMI and input voltage ripple. The proper

placement of the input capacitor (C6) can be seen in the

evaluation board layout in Figure 3. Additional noise fil-

tering for proper operation is accomplished by adding a

small 0.1μF capacitor on the IN pins (C2).

A laboratory test set-up typically consists of two long

wires running from the bench power supply to the eval-

uation board input voltage pins. The inductance of these

wires, along with the low-ESR ceramic input capacitor,

can create a high Q network that may affect converter

performance. This problem often becomes apparent in

the form of excessive ringing in the output voltage dur-

ing load transients. Errors in the loop phase and gain

measurements can also result. Since the inductance of a

short PCB trace feeding the input voltage is significantly

lower than the power leads from the bench power sup-

ply, most applications do not exhibit this problem. In

applications where the input power source lead induc-

tance cannot be reduced to a level that does not affect

the converter performance, a high ESR tantalum or alu-

minum electrolytic should be placed in parallel with the

low ESR, ESL bypass ceramic. This dampens the high Q

network and stabilizes the system.