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AAT1162

12V, 1.5A Step-Down DC/DC Converter

DATA SHEET

Output Capacitor Selection

The output capacitor is required to keep the output volt-

age ripple small and to ensure regulation loop stability.

The output capacitor must have low impedance at the

switching frequency. Ceramic capacitors with X5R or

X7R dielectrics are recommended due to their low ESR

mined by:

⎛⎞

· ESR +

Δ

⎝⎠

1

The output capacitor limits the output ripple and pro-

vides holdup during large load transitions. A 10μF to

47μF X5R or X7R ceramic capacitor typically provides

sufficient bulk capacitance to stabilize the output during

large load transitions and has the ESR and ESL charac-

teristics necessary for low output ripple. The output volt-

age droop due to a load transient is dominated by the

capacitance of the ceramic output capacitor. During a

step increase in load current, the ceramic output capac-

itor alone supplies the load current until the loop

responds. Within two or three switching cycles, the loop

responds and the inductor current increases to match

the load current demand. The relationship of the output

voltage droop during the three switching cycles to the

output capacitance can be estimated by:

Once the average inductor current increases to the DC

load level, the output voltage recovers. The above equa-

tion establishes a limit on the minimum value for the

output capacitor with respect to load transients. The

internal voltage loop compensation also limits the mini-

mum output capacitor value to 22μF. This is due to its

effect on the loop crossover frequency (bandwidth),

phase margin, and gain margin. Increased output capac-

itance will reduce the crossover frequency with greater

phase margin.

The maximum output capacitor RMS ripple current is

given by:

1

23

RMS(MAX)

I

=·

·

Dissipation due to the RMS current in the ceramic output

capacitor ESR is typically minimal, resulting in less than

a few degrees rise in hot-spot temperature.

Compensation

The AAT1162 step-down converter uses peak current

mode control with slope compensation scheme to main-

tain stability with lower value inductors for duty cycles

greater than 50%. The regulation feedback loop in the

IC is stabilized by the components connected to the

COMP pin, as shown in Figure 1.

To optimize the compensation components, the following

(R5) is calculated using the following equation:

output capacitor calculation.

determined from the following equation:

4

⎛⎞

10

The feed forward capacitor CFF (C1) provides faster

transient response for pulsed load applications. The

addition of the feed forward capacitor typically requires

a larger output capacitor C1 for stability. Larger C1 val-

ues reduce overshoot and undershoot during startup

and line/load changes. The CFF value can be from 100pF

to 470pF, but do not exceed 470pF to maintain stable

operation.