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201998B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 20, 2013

AAT1162

12V, 1.5A Step-Down DC/DC Converter

DATA SHEET

Layout Guidance

Figure 2 is the schematic for the evaluation board. When

laying out the PC board, the following layout guideline

should be followed to ensure proper operation of the

AAT1162:

1. Exposed pad EP1 must be reliably soldered to PGND/

DGND/AGND. The exposed thermal pad should be

connected to board ground plane and pins 6, 11, 13,

14 and 16. The ground plane should include a large

exposed copper pad under the package for thermal

dissipation.

2. The power traces, including GND traces, the LX

traces and the VIN trace should be kept short, direct

and wide to allow large current flow. The L1 connec-

tion to the LX pins should be as short as possible.

Use several via pads when routing between layers.

3. Exposed pad pin EP2 must be reliably soldered to the

LX pins 1 and 2. The exposed thermal pad should be

connected to the board LX connection and the induc-

tor L1 and also pins 1 and 2. The LX plane should

include a large exposed copper pad under the pack-

age for thermal dissipation.

4. The input capacitors (C9 and C1) should be con-

nected as close as possible to IN (Pins 4 and 5) and

DGND (Pin 6) to get good power filtering.

5. Keep the switching node LX away from the sensitive

FB node.

6. The feedback trace for the FB pin should be separate

from any power trace and connected as closely as

possible to the load point. Sensing along a high-

current load trace will degrade DC load regulation.

The feedback resistors should be placed as close as

possible to the FB pin (Pin 9) to minimize the length

of the high impedance feedback trace.

7. The output capacitors C3, 4, and 5 and L1 should be

connected as close as possible and there should not

be any signal lines under the inductor.

8. The resistance of the trace from the load return to

the PGND (Pin 16) should be kept to a minimum.

This will help to minimize any error in DC regulation

due to differences in the potential of the internal

signal ground and the power ground.