AM29F040 datasheet(13/33 Pages) AMD

13 / 33 page

Am29F040

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, the Am29F040 locks out write cycles

for VCC < VLKO (see DC Characteristics section for

voltages). When VCC < VLKO, the command register is

disabled, all internal program/erase circuits are

disabled, and the device resets to the read mode. The

Am29F040 ignores all writes until VCC > VLKO. The user

must ensure that the control pins are in the correct logic

state when VCC > VLKO to prevent unintentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE or

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,

CE = VIH or WE = VIH. To initiate a write cycle CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and

OE = VIH will not accept commands on the rising edge

of WE. The internal state machine is automatically

reset to the read mode on power-up.

Sector Protect

Sectors of the Am29F040 may be hardware protected

using programming equipment at the users factory. The

protection circuitry will disable both program and erase

functions for the protected sector(s). Requests to pro-

gram or erase a protected sector will be ignored by the

device.

AM29F040 数据表(PDF) 13 Page - Advanced Micro Devices