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AM79C940VCW 数据表(PDF) 102 Page - Advanced Micro Devices |
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AM79C940VCW 数据表(HTML) 102 Page - Advanced Micro Devices |
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102 / 122 page  AMD 102 Am79C940 AC WAVEFORMS 16235C-28 34 Word N Word N+1 Last Byte or Word 41 32 42 31 S3 S2 S1 S0 TH TL S0 S2 S1 S3 S1 S0 W1 W0 W1 W0 S2 S3 S0 W1 W0 SCLK (EDSEL = 1) R/ W DTV EOF DBUS[15:0] ADD[4:0] BE0-1 TC = 0 33 48 49 37 34 43 38 S3 S2 S1 S0 TH TL S0 S2 S1 S3 S1 S0 W1 W0 W1 W0 S2 S3 S0 W1 W0 SCLK (EDSEL = 0) CS Host System Interface—3-Cycle Transmit FIFO/Register Write Timing 16235C-29 EOF RDTREQ 39 44 SCLK (EDSEL = 1) S0 S2 S1 S3 S2 S1 S0 S2 S1 S3 S0 S0 S3 S2 45 Note 1 40 SCLK (EDSEL = 0) S0 S2 S1 S3 S2 S1 S0 S2 S1 S3 S0 S0 S3 S2 Note: Once the host detects the EOF output active from the MACE device (S2/S3 edge), if no other receive packet exists in the RCVFIFO which meets the assert conditions for RDTREQ, the MACE device will deassert RDTREQ within 4 SCLK cycles (S0/S1 edge). This is consistent for both 2 or 3 cycle read operations. Host System Interface—RDTREQ Read Timing |
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