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AM79C940VCW 数据表(PDF) 105 Page - Advanced Micro Devices |
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AM79C940VCW 数据表(HTML) 105 Page - Advanced Micro Devices |
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105 / 122 page ![]() AMD 105 Am79C940 16235C-34 0 V 100 mV Max 40 mV DO± 57 80 Bit Times Max AUI Transmit Timing—End Transmit Delimiter (ETD) 16235C-35 DI± RXCRS IVCO SRDCLK SRD IVCO_ENABLE (Note 1) BCC BCB BCC BCB BCC BCC BCB BCC BCB 5 Bit Times Max (Note 2) (Note 3) 10 1 0 1 0 Bit Cell 5 Bit Cell 4 Bit Cell 3 Bit Cell 2 Bit Cell 1 VASQ 59 60 Notes: 1. Minimum pulse width >45 ns with amplitude > –160 mV. 2. SRD first decoded bit might not be defined until bit time 5. 3. First valid data bit. 4. IVCO and VCO ENABLE are internal signals shown for clarification only. AUI Receive Timing—Start of Packet |
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