AM79C960KCW datasheet(71/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-413

Am79C960

RCVFW[1:0]

Bytes Received

Reserved

11-10XMTSP[1:0]

Transmit Start Point. XMTSP

controls the point at which pre-

amble

transmission

attempts

commence in relation to the num-

ber of bytes written to the

transmit FIFO for the current

transmit frame. When the entire

frame is in the FIFO, transmis-

sion will start regardless of the

value in XMTSP. XMTSP is given

a value of 10b (64 bytes) after

RESET. Regardless of XMTSP,

the FIFO will not internally over

write its data until at least 64

bytes (or the entire frame if <64

bytes) have been transmitted

onto the network. This ensures

that for collisions within the slot

time window, transmit data need

not be re-written to the transmit

FIFO, and re-tries will be handled

autonomously by the MAC. This

bit is read/write accessible only

when the STOP bit is set.

XMTSP[1:0]

Bytes Written

112

9-8 XMTFW[1:0]

Transmit

FIFO

Watermark.

XMTFW specifies the point at

which

transmit

DMA

stops,

based upon the number of write

cycles that could be performed to

the transmit FIFO without FIFO

overflow. Transmit DMA is al-

lowed at any time when the

number of write cycles specified

by XMTFW could be executed

without causing transmit FIFO

overflow. XMTFW is set to a

value of 00b (8 cycles) after hard-

ware

RESET.

Read/write

accessible only when STOP bit is

set.

XMTFW[1:0]

Write Cycles

Reserved

7-0

DMABR

DMA Burst Register. This regis-

ter

contains

the

maximum

allowable number of transfers to

system memory that the Bus In-

terface will perform during a

single DMA cycle. The Burst

number

transfers

during

Descriptor transfers. A value of

zero will be interpreted as one

transfer. During RESET a value

of 16 is loaded in the BURST reg-

ister. If DMAPLUS (CSR4.14) is

set, the DMA Burst Register is

disabled.

When the Bus Activity Timer reg-

ister

(CSR82:

DMABAT)

enabled, the PCnet-ISA control-

ler will relinquish the bus when

either

the

time

specified

DMABAT has elapsed or the

number of transfers specified in

DMABR have occured. When

ENTST (CSR4.15) is asserted,

all writes to this register will auto-

matically perform a decrement

cycle.

Read/write accessible only when

STOP bit is set.

CSR82: Bus Activity Timer

Bit

Name

Description

15-0 DMABAT

Bus Activity Timer. If the TIMER

bit in CSR4 is set, this register

contains the maximum allowable

time that the PCnet-ISA control-

ler will take up on the system bus

during FIFO data transfers in

each bus mastership period. The

DMABAT starts counting upon

receipt of

DACK from the host

system. The DMABAT Register

does not limit the number of

transfers

during

Descriptor

transfers.

A value of zero will limit the

PCnet-ISA controller to one bus

cycle per mastership period. A

non-zero value is interpreted as

an unsigned number with a reso-

lution of 100 ns. For instance, a

value of 51 micro seconds would

be programmed with a value of

510. When the TIMER bit in

CSR4 is set, DMABAT is enabled

and must be initialized by the

user. The DMABAT register is

undefined until written. When the

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