AM79C960KCW datasheet(17/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-359

Am79C960

BABL

Babble

RCVCCO

Receive Collision Count Overflow

JAB

Jabber

MISS

Missed Frame

MERR

Memory Error

MFCO

Missed Frame Count Overflow

RINT

Receive Interrupt

IDON

Initialization Done

TXSTRT

Transmit Start

LA17-23

Unlatched Address Bus

Output

The unlatched address bus is driven by the PCnet-ISA

controller during bus master cycle.

The functions of these unlatched address pins will

change when GPSI mode is invoked. The table below

shows the pin configuration in GPSI mode. Please refer

to the section on General Purpose Serial Interface for

detailed information on accessing this mode.

Pin Function in

Number

Bus Master Mode

GPSI Mode

LA17

RXDAT

LA18

SRDCLK

LA19

RXCRS

LA20

CLSN

LA21

STDCLK

LA22

TXEN

LA23

TXDAT

MASTER

Master Mode

Output

This signal indicates that the PCnet-ISA controller has

become the Current Master of the ISA bus. After the

PCnet-ISA controller has received a DMA Acknowledge

(

DACK) in response to a DMA Request (DRQ), the

Ethernet controller asserts the

MASTER signal to indi-

cate to the Permanent Master that the PCnet-ISA

controller is becoming the Current Master.

MEMR

Memory Read

Output

MEMR goes LOW to perform a memory read operation.

MEMW

Memory Write

Output

MEMW goes LOW to perform a memory write

operation.

REF

Memory Refresh

Input

When

REF is asserted, a memory refresh is active. The

PCnet-ISA controller uses this signal to mask inadver-

tent DMA Acknowledge assertion during memory

refresh periods. If

DACK is asserted when REF is ac-

tive,

DACK assertion is ignored. REF is monitored to

eliminate a bus arbitration problem observed on some

ISA platforms.

RESET

Reset

Input

When RESET is asserted HIGH the PCnet-ISA control-

ler performs an internal system reset. RESET must be

held for a minimum of 10 XTAL1 periods before being

deasserted. While in a reset state, the PCnet-ISA con-

troller will tristate or deassert all outputs to predefined

reset levels. The PCnet-ISA controller resets itself upon

power-up.

SA0-19

System Address Bus

Input/Output

This bus contains address information, which is stable

during a bus operation, regardless of the source.

SA17-19 contain the same values as the unlatched ad-

dress LA17-19. When the PCnet-ISA controller is the

Current Master, SA0-19 will be driven actively. When

the PCnet-ISA controller is not the Current Master, the

SA0-19 lines are continuously monitored to determine if

an address match exists for I/O slave transfers or Boot

PROM accesses.

SBHE

System Byte High Enable

Input/Output

This signal indicates the high byte of the system data

bus is to be used.

SBHE is driven by the PCnet-ISA con-

troller when performing bus mastering operations.

SD0-15

System Data Bus

Input/Output

These pins are used to transfer data to and from the

PCnet-ISA controller to system resources via the ISA

data bus. SD0-15 is driven by the PCnet-ISA controller

when performing bus master writes and slave read op-

erations. Likewise, the data on SD0-15 is latched by the

PCnet-ISA controller when performing bus master

reads and slave write operations.

SMEMR

System Memory Read

Input

This pin is used during Boot PROM access. The Boot

PROM can be disabled by not connecting this pin.

Board Interface

APCS

Address PROM Chip Select

Output

This signal is asserted when the external Address

PROM is read. When an I/O read operation is per-

formed on the first 16 bytes in the PCnet-ISA controller’s

I/O space,

APCS is asserted. The outputs of the exter-

nal Address PROM drive the PROM Data Bus. The

PCnet-ISA controller buffers the contents of the PROM

data bus and drives them on the lower eight bits of the

System Data Bus.

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