AM79C960KCW datasheet(18/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-360

Am79C960

BPCS

Boot PROM Chip Select

Output

This signal is asserted when the Boot PROM is read. If

SA0-19 lines match a predefined address block and

SMEMR is active and REF inactive, the BPCS signal will

be asserted. The outputs of the external Boot PROM

drive the PROM Data Bus. The PCnet-ISA controller

buffers the contents of the PROM data bus and drives

them on the lower eight bits of the System Data Bus.

DXCVR

Disable Transceiver

Output

This pin disables the transceiver. The DXCVR output is

configured in the initialization sequence. A HIGH level

indicates the Twisted Pair port is active and the AUI port

is inactive, or SLEEP mode has been entered. A LOW

level indicates the AUI port is active and the Twisted Pair

port is inactive.

IOAM0-1

Input/Output Address Map

Input

These inputs configure I/O address space for the

PCnet-ISA controller and memory address space for the

optional Remote Boot PROM with user selectable jump-

ers. The pins are pulled HIGH internally. The SA1-9

inputs are used for I/O address comparisons and the

SA14-19 inputs are used for Boot PROM matching.

IOAM1,0

I/O Base

Memory Base

0 0

300 Hex

C8000 Hex

0 1

320 Hex

CC000 Hex

1 0

340 Hex

D0000 Hex

1 1

360 Hex

D4000 Hex

LED0-3

LED Drivers

Output

These pins sink 12 mA each for driving LEDs. Their

meaning is software configurable (see section

ISA Bus

Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named

LED1,

LED2, and LED3 change in function while LED0 contin-

ues to indicate 10BASE-T Link Status. The MAUSEL

input becomes the

EAR input.

LED

EADI Function

SF/BD

SRD

SRDCLK

MAUSEL/EAR

MAU Select/

External Address Reject

Input

This pin selects the 10BASE-T MAU when HIGH and

the AUI interface when LOW if the XMAUSEL register

bit in ISACSR2 (ISA Configuration Register) is set. If the

XMAUSEL register bit is cleared, the MAUSEL pin is ig-

nored and the network interface is software selected.

This pin has a default value of HIGH if left unconnected.

If EADI mode is selected, this pin becomes the

EAR

input. The incoming frame will be checked against the

internally active address detection mechanisms and the

result of this check will be OR’d with the value on the

EAR pin. The EAR pin is defind as REJECT. See the

EADI section for details regarding the function and tim-

ing of this signal.

PRDB0-7

Private Data Bus

Input

This is the data bus for the Boot PROM and the Address

PROM.

SLEEP

Sleep

Input

When

SLEEP pin is asserted (active LOW), the PCnet-

ISA controller performs an internal system reset and

proceeds into a power savings mode. All outputs will be

placed in their normal reset condition. All PCnet-ISA

controller inputs will be ignored except for the

SLEEP

pin itself. Deassertion of

SLEEP results in wake-up.

The system must delay the starting of the network con-

troller by 0.5 seconds to allow internal analog circuits to

stabilize.

Test Enable

Input

This pin is for factory use only. It has a default value of

HIGH if left unconnected. It is recommended that this pin

always be connected to VDD.

XTAL1

Crystal Connection

Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. Refer to the section on External

Crystal Characteristics for more details.

XTAL2

Crystal Connection

Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

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AM79C960KCW 数据表(PDF) 18 Page - Advanced Micro Devices

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