AM79C976 datasheet(39/309 Pages) AMD

39 / 309 page

8/01/00

Am79C976

P R E L I M INARY

)LJXUH 'LVFRQQHFW 2I6ODYH %XUVW 7UDQVIHU

+RVW,QVHUWV :DLW6WDWHV

3DULW\ (UURU5HVSRQVH

When the Am79C976 controller is not the current bus

master, it samples the AD[31:0], C/BE[3:0], and the

PAR lines during the address phase of any PCI com-

mand for a parity error. When it detects an address par-

ity error, the controller sets PERR (PCI Status register,

bit 15) to 1. When reporting of that error is enabled by

setting SERREN (PCI Command register, bit 8) and

PERREN (PCI Command register, bit 6) to 1, the

Am79C976 controller also drives the SERR signal low

for one clock cycle and sets SERR (PCI Status register,

bit 14) to 1. The assertion of SERR follows the address

phase by two clock cycles. The Am79C976 controller

will not assert DEVSEL for a PCI transaction that has

an address parity error when PERREN and SERREN

are set to 1. See Figure 88.

)LJXUH $GGUHVV3DULW\ (UURU 5HVSRQVH

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that selects

the Am79C976 controller as target, the device samples

the AD[31:0] and C/BE[3:0] lines for parity on the clock

edge, and data is transferred as indicated by the asser-

tion of IRDY and TRDY. PAR is sampled in the following

clock cycle. If a parity error is detected and reporting of

that error is enabled by setting PERREN (PCI Com-

mand register, bit 6) to 1, PERR is asserted one clock

later. The parity error will always set PERR (PCI Status

0. The Am79C976 controller will finish a transaction

that has a data parity error in the normal way by assert-

ing TRDY. The corrupted data will be written to the

addressed location.

Figure 9 shows a transaction that suffered a parity error

at the time data was transferred (clock 7, IRDY and

TRDY are both asserted). PERR is driven high at the

beginning of the data phase and then drops low due to

the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C976 controller drives PERR high for one clock

cycle, since PERR is a sustained tri-state signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

23456

PAR

DATA

1st DATA

22929B9

FRAME

CLK

SERR

C/BE

DEVSEL

2345

PAR

ADDR

1st DATA

CMD

PAR

22929B10

AM79C976 数据表(PDF) 39 Page - Advanced Micro Devices

AM79C976 数据表(HTML) 39 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载