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AM79C976 数据表(PDF) 49 Page - Advanced Micro Devices |
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AM79C976 数据表(HTML) 49 Page - Advanced Micro Devices |
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49 / 309 page  8/01/00 Am79C976 49 P R E L I M INARY )LJXUH3UHHPSWLRQ'XULQJ1RQ%XUVW7UDQVDFWLRQ If the controller is executing a Memory Write and Inval- idate instruction when preemption occurs, the control- ler will finish writing the current cache line before it releases the bus. Figure 19 assumes that the PCI Latency Timer has counted down to 0 on clock 7. 0DVWHU $ERUW The Am79C976 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C976 controller. The Am79C976 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI con- figuration registers will not be cleared. Any on-going network transmission is terminated in an orderly se- quence. The message will have the current FCS in- verted and appended at the next byte boundary to guarantee that the receiving station will treat the trans- mission either as a runt or as a corrupted frame. RMABORT (in the PCI Status register, bit 13) will be set to indicate that the Am79C976 controller has termi- nated its transaction with a master abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INTA is asserted if the enable bit SINTE (CSR5, bit 10) is set to 1. This mechanism can be used to inform the driver of the system error. The host can read the PCI Status register to determine the exact cause of the in- terrupt. See Figure 2020. FRAME CLK AD IRDY TRDY C/BE DEVSEL REQ GNT 1 234567 BE 0111 PAR PAR DEVSEL is sampled PAR DATA ADDR 22929B20 |
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