AM79C976 datasheet(63/309 Pages) AMD

63 / 309 page

8/01/00

Am79C976

P R E L I M INARY

Note that in this mode the value of CSR2, bits 15-8, is

used as the upper 8-bits for all memory addresses dur-

ing bus master transfers.

Figure 29 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is set to 1.

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If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C976 controller, then the

Am79C976 controller will periodically poll the current

receive and transmit descriptor entries in order to as-

certain their ownership. If the TXDPOLL bit in CSR4 is

set, then the transmit polling function is disabled. The

Descriptor Management Unit (DMU) is responsible for

these operations.

The Am79C976 controller stores internally the informa-

tion from two or more receive descriptors and two or

more transmit descriptors. Polling operations depend

on the ownership of the current and next receive and

transmit descriptors.

When the poll time has elapsed, if the current receive

descriptor is not owned by the Am79C976 controller or

if the current receive descriptor is owned and the next

receive descriptor is not owned, the unowned descrip-

tor will be polled. Depending on the software style,

more than one descriptor may be read in a burst.

If the TXDPOLL bit is not set and the poll time has

elapsed, or whenever the TDMD bit is set, if the current

transmit descriptor is not owned by the Am79C976

controller, it will be polled. Depending on the software

style, more than one descriptor may be read in a burst.

If either transmit or receive or both are suspended or

disabled due to the setting of TX_SPND, RX_SPND,

SPND, DRX or DTX, the corresponding descriptors will

not be polled. Polling is not affected by fast suspend.

Initialization

Block

CSR1

CSR2

RMD0

RMD1

RMD2 RMD3

Rcv Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

RMD0

TMD0

TMD1 TMD2 TMD3

Xmt Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16]

IADR[15:0]

TLE RES RLE RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

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