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AM79C976 数据表(PDF) 47 Page - Advanced Micro Devices |
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AM79C976 数据表(HTML) 47 Page - Advanced Micro Devices |
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47 / 309 page ![]() 8/01/00 Am79C976 47 P R E L I M INARY )LJXUH 'LVFRQQHFW:LWKRXW'DWD7UDQVIHU 7DUJHW$ERUW Figure 17 shows a target abort sequence. The target asserts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it can- not service the data transfer and that it does not want the transa ctio n to be retr ied. Ad ditio nally, the Am79C976 controller cannot make any assumption about the success of the previous data transfers in the current transaction. The Am79C976 controller termi- nates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock cycle later. It finally releases the bus on clock 6. Since data integrity is not guaranteed, the Am79C976 controller cannot recover from a target abort event. The Am79C976 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI configuration registers will not be cleared. Any on-going network transmission is terminated with the current FCS invert- ed and appended at the next byte boundary. This guar- antees that the receiving station will drop the truncated frame. FRAME CLK AD IRDY TRDY C/BE DEVSEL REQ GNT PAR DEVSEL is sampled STOP ADDRi 0000 0111 PAR 0111 2 3456789 11 10 ADDRi DATA PAR 1 22929B18 |
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