A7986ATR datasheet(25/42 Pages) STMICROELECTRONICS

25 / 42 page

DocID022801 Rev 5

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A7986A

Application information

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follows:

Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4

and C5 not comparable with parasitic capacitance of the board.

Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 30

where fESR is the ESR zero:

Equation 31

and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio Vs/Vin constant.

Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 32

Then calculate C3 in order to place the second pole at four times the system bandwidth

(BW):

Equation 33

For example with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 μH, COUT = 330 μF, and ESR = 35

Ω, the Type II compensation network is:

In Figure 15, the module and phase of the open loop gain is shown. The bandwidth is about

21 kHz and the phase margin is 45°.

ESR

------------





ES R

------------

--------- R

⋅⋅

⋅

ESR

π ESR C

OUT

⋅⋅

--------------------------------------------

π R

⋅⋅

-------------------------------

π R

4BW

⋅

–

⋅⋅

⋅

--------------------------------------------------------------

1.1k

150

4.99k

82nF

68pF

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