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STM8S005C6T6 数据表(PDF) 39 Page - STMicroelectronics |
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STM8S005C6T6 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 103 page  Reset status Register name Register label Block Address 0x00 ADC low threshold register high ADC_LTRH 0x00 540A 0x00 ADC low threshold register low ADC_LTRL 0x00 540B 0x00 ADC analog watchdog status register high ADC_AWSRH 0x00 540C 0x00 ADC analog watchdog status register low ADC_AWSRL 0x00 540D 0x00 ADC analog watchdog control register high ADC _AWCRH 0x00 540E 0x00 ADC analog watchdog control register low ADC_AWCRL 0x00 540F Reserved area (1008 bytes) 0x00 5410 to 0x00 57FF (1) Depends on the previous reset source. (2) Write only register. CPU/SWIM/debug module/interrupt controller registers 6.2.3 Table 9: CPU/SWIM/debug module/interrupt controller registers Reset status Register name Register label Block Address 0x00 Accumulator A CPU (1) 0x00 7F00 0x00 Program counter extended PCE 0x00 7F01 0x00 Program counter high PCH 0x00 7F02 0x00 Program counter low PCL 0x00 7F03 0x00 X index register high XH 0x00 7F04 39/103 DocID022186 Rev 3 Memory and register map STM8S005K6 STM8S005C6 |
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