STM8S005C6T6 datasheet(44/103 Pages) STMICROELECTRONICS

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Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP

option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication

protocol and debug module user manual (UM0470) for information on SWIM programming

procedures.

Table 11: Option bytes

Factory

default

setting

Option bits

Option

byte no.

Option

name

Addr.

00h

ROP [7:0]

OPT0

Read-out

protection

(ROP)

0x4800

00h

UBC [7:0]

OPT1

User boot

code(UBC)

0x4801

FFh

NUBC [7:0]

NOPT1

0x4802

00h

AFR0

AFR1

AFR2

AFR3

AFR4

AFR5

AFR6

AFR7

OPT2

Alternate

function

0x4803

FFh

NAFR0

NAFR1

NAFR2

NAFR3

NAFR4

NAFR5

NAFR6

NAFR7

NOPT2

0x4804

remapping

(AFR)

00h

WWDG

_HALT

WWDG

_HW

IWDG

_HW

LSI_ EN

HSI

TRIM

Reserved

OPT3

Miscell.

option

0x4805h

FFh

NWW

G_HALT

NWWDG

_HW

NIWDG

_HW

NLSI_

NHSI

TRIM

Reserved

NOPT3

0x4806

00h

PRS C0

PRS C1

CKAWU

SEL

EXT CLK

Reserved

OPT4

Clock

option

0x4807

FFh

NPR

SC0

NPRSC1

NCKA

WUSEL

CLK

Reserved

NOPT4

0x4808

00h

HSECNT [7:0]

OPT5

HSE clock

startup

0x4809

FFh

NHSECNT [7:0]

NOPT5

0x480A

00h

Reserved

OPT6

Reserved

0x480B

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STM8S005K6 STM8S005C6

Option bytes

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