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STM32F107VC 数据表(PDF) 68 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 103 page  Electrical characteristics STM32F105xx, STM32F107xx 68/104 Doc ID 15274 Rev 6 Table 44. I2S characteristics Symbol Parameter Conditions Min Max Unit fCK 1/tc(CK) I2S clock frequency Master data: 16 bits, audio freq = 48 K 1.52 1.54 MHz Slave 0 6.5 tr(CK) tf(CK) I2S clock rise and fall time capacitive load CL = 50 pF 8 ns tw(CKH) (1) I2S clock high time Master fPCLK = 16 MHz, audio freq = 48 K 317 320 tw(CKL) (1) I2S clock low time 333 336 tv(WS) (1) WS valid time Master mode 3 th(WS) (1) WS hold time Master mode I2S2 0 I2S3 0 tsu(WS) (1) WS setup time Slave mode I2S2 4 I2S3 9 th(WS) (1) WS hold time Slave mode 0 DuCy(SCK) I2S slave input clock duty cycle Slave mode 30 70 % tsu(SD_MR) (1) Data input setup time Master receiver I2S2 8 ns I2S3 10 tsu(SD_SR) (1) Slave receiver I2S2 3 I2S3 8 th(SD_MR) (1) Data input hold time Master receiver I2S2 2 I2S3 4 th(SD_SR) (1) Slave receiver I2S2 2 I2S3 4 tv(SD_ST) (1)(3) Data output valid time Slave transmitter (after enable edge) I2S2 23 I2S3 33 th(SD_ST) (1) Data output hold time Slave transmitter (after enable edge) I2S2 29 I2S3 27 tv(SD_MT) (1) Data output valid time Master transmitter (after enable edge) I2S2 5 I2S3 2 th(SD_MT) (1) Data output hold time Master transmitter (after enable edge) I2S2 11 I2S3 4 1. Based on design simulation and/or characterization results, not tested in production. |
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