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STM32F107VC 数据表(PDF) 92 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 103 page  Application block diagrams STM32F105xx, STM32F107xx 92/104 Doc ID 15274 Rev 6 Figure 48. OTG connection (any protocol) 1. STMPS2141STR needed only if the application has to support bus-powered devices. A.2 Ethernet interface solutions Figure 49. MII mode using a 25 MHz crystal 1. HCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP, optional signal. USB OTG Full-speed core STM32F105xx/STM32F107xx USB full-speed/ low-speed transceiver DP DM VBUS VSS HNP HNP SRP SRP ID ID OTG PHY ai15655b GPIO GPIO + IRQ EN Current-limited power distribution switch STMPS2141STR (1) ID OVRCR flag VDD 5 V MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 25 MHz MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MDIO MDC HCLK(1) PPS_OUT(2) XTAL 25 MHz STM32F107xx OSC TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP MII = 15 pins MII + MDC = 17 pins ai15656 |
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