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STM32F415RG 数据表(PDF) 102 Page - STMicroelectronics |
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STM32F415RG 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 186 page  Electrical characteristics STM32F415xx, STM32F417xx 102/186 DocID022063 Rev 4 Table 35. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95(2) 12.10 MHz fPLL_OUT PLL multiplier output clock 24 - 168 MHz fPLL48_OUT 48 MHz PLL multiplier output clock -48 75 MHz fVCO_OUT PLL VCO output 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples -32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples -40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 12.10 MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 |
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